Stmicroelectronics S.r.l.

Stmicroelectronics (Beijing) R&d Company Ltd.

Stmicroelectronics (Bejing) R&d Company Ltd.

HongXia Sun

PengFei Zhu

Elio Guidetti

YongQiang Wu

Yongqiang Wu

Kai Wang

Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.

Modified balanced throughput data-path architecture for special correlation applications

An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.

Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture

A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

Register file organization to share process context for heterogeneous multiple processors or joint processor

In mesh networks having multiple nodes that communicate data to and from each other, a great number of data transmissions may be initiated and carried out to get data to a proper processing node for execution. To get data where it needs to go (e.g., the proper destination node), a routing algorithm is used to define a set of rules for efficiently passing data from node to node until the destination node is reached. For the purpose of assuring that all data is properly transferred from node to node in a reasonably efficient manner, a routing algorithm may define subsets of nodes into regions and then send data via the regions. Even greater overall efficiency may be realized by recognizing specific adjacency relationships among a group of destination nodes and taking advantage of such adjacencies by rerouting data through regions other than the region in which a destination node resides.

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Bejing, China

HongXia Sun