Lsi Corporation

Marvell International Limited

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Hongwei Song

George Mathew

Yuan Xing Lee

Shaohua Yang

Jingfeng Liu

Zining Wu

Weijun Tan

Lingyan Sun

Gregory Burd

Xueshi Yang

Richard Rauschmayer

Yu Liao

Haotian Zhang

Michael Madden

Jeffrey Paul Grundvig

Ke Han

Hongxin Song

Yifei Zhang

Nedeljko Varnica

Viswanath Annampedu

Jin Xie

Xun Zhang

Jongseung Park

Zachary A Keirn

Toai Doan

Jefferson E Singleton

Suharli Tedja

Peter Stroud

Haitao Xia

Hao Zhong

Jonathan James Ashley

Kelly K Fitzpatrick

Scott M Dziak

German S Feyh

Fan Zhou

Robert Alan Greene

Pradeep Padukone

YuanXing Lee

Jinfeng Liu

Liu Jingfeng

David L Parker

Xia Haitao

Various embodiments of the present invention provide systems and methods for determining changes in fly-height. For example, various embodiments of the present invention provide storage devices that include a storage medium having servo data thereon. A read/write head assembly is disposed in relation to the storage medium. A servo based fly-height adjustment circuit receives the servo data via the read/write head assembly, and calculates a first harmonics ratio based on the received data and compares the first harmonics ratio with a second harmonics ratio to determine an error in the distance between the read/write head assembly and the storage medium.

Systems and methods for fly-height control using servo data

Various embodiments of the present invention provide systems and methods for estimating signal and noise powers in a received signal set. For example, one embodiment of the present invention provides a method for determining signal power and noise power. The method uses a storage medium that includes a N&#xd7;Ndata pattern. The N&#xd7;Ndata pattern includes Nbits repeated Ntimes. Both Nand Nare each greater than one. The methods further include performing an initial read of the N&#xd7;Ndata pattern, which is stored to a first register. Nsubsequent reads of the N&#xd7;Ndata pattern are each processed by: performing a subsequent read of the N&#xd7;Ndata pattern, and performing a difference calculation using the initial read of the N&#xd7;Ndata pattern and the subsequent read of the N&#xd7;Ndata pattern and resulting in the calculation of a difference vector that is stored to a second register; and performing a difference accumulation calculation to generate an accumulation vector which is stored to a third register. Based at least in part on the stored N&#xd7;Ndata pattern and the stored difference vector, an electronics noise power is calculated.

Systems and methods for memory efficient signal and noise estimation

Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

Systems and methods for filter constraint estimation

A QC-LDPC decoding system employing a trapping set look-up table is provided. The QC-LDPC decoding system includes an iterative decoder that utilizes a message-passing algorithm to decode a received codeword. If the iterative decoder fails to produce a valid codeword, additional processing is performed to decode the received codeword. The additional processing includes the steps of computing the syndrome pattern of the received codeword, searching the look-up table for a trapping set class that is responsible for the iterative decoder's failure, retrieving from the look-up table a syndrome pattern and an error pattern of a member of the responsible trapping set class, and calculating the error pattern of the received codeword based on its syndrome pattern and the information retrieved from the look-up table. The received codeword is then corrected based on its error pattern.

QC-LDPC decoder with list-syndrome decoding

An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. In some embodiments, on the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. At least a portion of the first set of codewords preferably is divided into a plurality of symbols which are encoded based on the embedded parity code to provide encoded data. Similarly, in some embodiments, on the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information preferably is used, together with other soft information, by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

Error correction system using an iterative product code

A channel decoder includes a demodulator, a filter, a detector module, and first and second circuits. The demodulator receives an input signal based on data read from a storage medium, and demodulates the input signal to generate a data signal. The filter generates equalized data based on the data signal. The detector module executes a Viterbi algorithm based on the equalized data to generate estimates of data originally stored in the storage medium, and based on the execution of the Viterbi algorithm, generates a first and second sets of depths. The first set of depths includes depths larger than depths in the second set of depths. The first circuit generates a first error signal based on the first set of depths. The second circuit generates a second error signal based on the second set of depths. The filter generates the equalized data based on the first and second error signals.

Channel decoder and method for generating equalized data and data estimates based on multiple sets of depths provided via a viterbi algorithm

Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

Nyquist constrained digital finite impulse response filter

A system including a storage medium, a demodulator, and a decoder. The demodulator is configured to receive an input signal from the storage medium and demodulate the input signal. The decoder is configured to estimate data stored in the storage medium by decoding the demodulated input signal to provide an output signal. The decoder includes a filter and first and second processors. The filter is configured to generate a first equalized signal based on the output signal. The first processor is configured to, based on the first equalized signal and a first Viterbi algorithm, generate a first estimate of the data and an estimate of noise. The second processor is configured to generate a second estimate of the data based on the first estimate of the data, the estimate of the noise, and a second Viterbi algorithm. The output signal includes the second estimate of the data.

Method and apparatus for using dual-viterbi algorithms to estimate data stored in a storage medium

A system for identifying and compensating for non-linear transition shift in a magnetic medium data storage device is disclosed. The non-linear transition shift compensation system includes a non-linear transition shift estimation module adapted to generate non-linear transition shift estimates for specific bit patterns. The system further includes a pre-compensation module adapted to adjust the temporal spacing of binary transitions written to the magnetic medium based on the non-linear transition shift estimates generated by the non-linear transition shift estimation module for specific bit patterns corresponding to bit patterns appearing in the data being written to the magnetic medium.

Non-linear transition shift identification and compensation

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

Systems and methods for auto scaling in a data processing system

Various embodiments of the present invention provide systems and methods for reducing filter sensitivities. As an example, reduced sensitivity filter circuits are discussed that include a digital filter and a filter tap adaptation circuit. The digital filter is operable to filter a received input based at least in part on a plurality of filter taps, and to provide a filtered output. The filter tap adaptation circuit is operable to receive an error value and a weighting control value, and to adaptively calculate at least one of the filter taps using the error value and the weighting control value.

Systems and methods for reducing filter sensitivities

Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media noise power output each calculated based at least in part on the detected output and the series of data samples.

Systems and methods for determining noise components in a signal set

Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Systems and methods for adaptive target search

A method for detecting a data sequence includes generating a first sample stream, which is a time-sequenced digital signal associated with samples of an analog signal. The first sample stream is interpolated to generate a second sample stream with a different phase. The first sample stream is equalized to generate a first equalized sample stream. The second sample stream is equalized to generate a second equalized sample stream. The first and second equalized sample streams are processed to estimate the second equalized sample stream. The first equalized sample stream is filtered to generate a first set of noise sample streams. The estimated second equalized sample stream is filtered to generate a second set of noise sample streams. The first set and the second set of noise sample streams are diversity combined to generate a set of combined noise sample streams. A data sequence is detected using the combined noise sample streams.

Data sequence detection in band-limited channels based on equalization interpolation

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output.

Systems and methods for reliability assisted noise predictive filtering

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Longmont, CO, United States of America

Hongwei Song