Inspur Suzhou Intelligent Technology Co., Ltd

Suzhou Metabrain Intelligent Technology Co., Ltd.

Hongwei Kan

Rengang Li

Jiangwei Wang

Yanwei Wang

Rui Hao

Jiaheng Fan

Jingdong Zhang

Nan Wu

Weifeng Gong

Mingyang Ou

Yaming Xu

Linge Xiao

Dongdong Su

Le Yang

Kefeng Zhu

Provided are a communication method and system for a distributed heterogeneous acceleration platform, a device and a medium. The method includes: after starting a collaborative acceleration task, determining, by a first target heterogeneous acceleration card in a distributed heterogeneous acceleration platform, a second target heterogeneous acceleration card from the distributed heterogeneous acceleration platform by querying an information table corresponding to the collaborative acceleration task; generating, by the first target heterogeneous acceleration card, a target data packet according to a predefined data packet format, and sending the target data packet to the second target heterogeneous acceleration card via a PCIE interface; and parsing, by the second target heterogeneous acceleration card, the target data packet according to the data packet format, and executing a corresponding read operation or write operation according to a parsing result, so as to complete the collaborative acceleration task.

Communication method and system for distributed heterogeneous acceleration platform, device and medium

A data processing method, a data processing apparatus, a distributed data flow programming framework, an electronic device, and a storage medium. The data processing method includes: dividing a data processing task into a plurality of data processing subtasks (S); determining, in a Field Programmable Gate Array (FPGA) accelerator side, a target FPGA acceleration board corresponding to each of the data processing subtasks (S); and sending data to be computed to the target FPGA acceleration board, and executing the corresponding data processing subtask by use of each of the target FPGA acceleration boards to obtain a data processing result (S). According to the method, a physical limitation of host interfaces on the number of FPGA acceleration boards in an FPGA accelerator side may be avoided, thereby improving the data processing efficiency.

Data processing method and apparatus, distributed data flow programming framework, and related component

The present disclosure relates to data processing, and in particular, to a system for processing a full-stack network card task based on FPGA. The system includes: a network interface controller, configured to receive to-be-processed data, and offload a TCP/IP task from the to-be-processed data by a built-in TCP offload engine, to obtain first processed data; an SSL/TLS protocol processing module, configured to receive the first processed data, and offload an SSL/TLS protocol task from the first processed data, to obtain second processed data; a PR region, configured to receive the second processed data; and a reconfiguration module, configured to acquire, by a host, dynamic configuration information of the PR region, and configure the PR region based on the dynamic configuration information, so that the PR region offloads and processes computation-intensive tasks in the second processed data.

Method and system for processing full-stack network card task based on FPGA

A heterogeneous acceleration method, including the following steps: analyzing a received target data packet to obtain data source end identification information; when the data source end identification information does not exist in a configuration information table, customizing a data message format according to the target data packet to obtain a target data message format, or when the data source end identification information exists in the configuration information table, reading the target data message format from the configuration information table; and according to the target data message format, performing acceleration processing on the target data packet to obtain processed data, and returning the processed data to a data source end.

Heterogeneous acceleration method, apparatus and system and computer readable storage medium

A far-end data migration device and method based on a FPGA cloud platform. The device includes a server, a switch, and a plurality of FPGA acceleration cards. The server transmits data to be accelerated to the FPGA acceleration cards by means of the switch. The FPGA acceleration cards are configured to perform a primary and/or secondary acceleration on the data, and are configured to migrate the accelerated data. The method includes: transmitting data to be accelerated to a FPGA acceleration card from a server by means of a switch; performing, by the FPGA acceleration card, a primary and/or secondary acceleration on the data to be accelerated; and migrating, by the FPGA acceleration card, the accelerated data.

Far-end data migration device and method based on FPGA cloud platform

A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

Method and apparatus for performing power stress test on FPGA acceleration card, and storage medium

Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S).

Growing community of inventors

Jiangsu, China

Hongwei Kan