Boe Technology Group Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Institute of Geology and Geophysics

Hongwei Gao

Guoqing Zhang

Pucha Zhao

Xiaowei Wang

Xiaopeng Bai

Weifeng Wang

Hongxia Yang

Ke Zhao

Yan Zong

Zhihui Jia

Yaorong Liu

Wei Liu

Tao Yang

Jin Zhao

Shanshan Bao

Jianfeng Zhang

Xinxin Jin

Haotian Chen

Yuebai Han

Yanbin Dang

Longfei Yang

Zhixin Guo

Meili Guo

Linong Liu

Mingyang Zhang

A data optimization method and an integral prestack depth migration method are provided, including acquiring a target matrix to be optimized; generating a first sequence according to the target matrix; rarefying the first sequence according to a preset grid density to obtain a value position of each element of a second sequence, and working out a value of each element of the second sequence on the basis of the principle of least squares; performing interpolation on the second sequence to obtain a third sequence; calculating a target matrix corresponding to the third sequence; calculating an error between the target matrix to be optimized and the target matrix corresponding to the third sequence; recording, when the error is less than the first error threshold, the target matrix corresponding to the above second sequence as an optimized target matrix of the target matrix to be optimized.

Data optimization method and integral prestack depth migration method

A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.

Test circuitry and method for testing the same, test system

The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.

Method and system for aging process on transistors in a display panel

The present disclosure belongs to the field of display technology, and particularly relates to a test circuit, a display substrate, a test method of a display substrate and a display apparatus. The test circuit includes a signal generating device and a plurality of output channels that are mutually independent. Each output channel includes a signal line configured to transmit a test signal. The signal generating device is coupled to the plurality of output channels, and is configured to provide, to each of at least one of the plurality of output channels, the test signal corresponding to an impedance of the signal line in the output channel, and provide the test signal to the signal line in the output channel.

Test circuit, display substrate, test method thereof and display apparatus

A set of measurement voltages having different voltage values are subsequently inputted to a measurement voltage input terminal of the pixel driving circuit, a light emitting state of a light emitting device under each measurement voltage is detected, and it is determined whether a storage capacitor in the pixel driving circuit is normal based on the light emitting state of the light emitting device.

Capacitor detection method and pixel driving circuit

The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I&#x3c;IT&#x2264;IF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.

Circuit board and method for manufacturing the same, terminal test device

Embodiments of the present disclosure provide a test circuit, a test method, a display panel and a display apparatus. Each of the signal input terminals may input a plurality of signals in a time division multiplexed manner, and in turn may be controlled by the corresponding switches to form a plurality of signal lines, a signal flow of the plurality of signal lines are totally different from each other under control of the switches. For example, one of the signal lines may function as a signal input line, and the other one of the signal lines may function as a signal input line for other specific testing, such as aging process so as to input signals different from the normal turn-on state signals. Consequently, by controlling the corresponding switches through the control signal terminals so that different input signals pass through different signal lines into the display panel to meet testing requirements of normal turn-on state testing, aging process and so on for the display panel. With respect to the prior art, the testing signals may be input without passing through a shift register unit, which avoids damage of a specific testing signal such as aging signal on the shift register unit and ensure a normal displaying function of the display panel.

Test circuit, test method, display panel and display apparatus

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Beijing, China

Hongwei Gao