Skhynix Inc.

Hongwei Duan

Fan Zhang

Haobo Wang

Aman Bhatia

Meysam Asadi

Chenrong Xiong

Michael Hsu

Jiangnan Xia

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, and performing, on the noisy codeword, a message passing algorithm. As part of the message passing algorithm, a check node is configured to receive each of multiple messages from a corresponding variable node connected to the check node. Then, the check node identifies, based on the multiple messages, check node unit (CNU) parameters, and maps a concatenation of the CNU parameters to a bit string that has a length less than that of the concatenation. The bit string, which is a compressed form of the CNU parameters, is stored in a CNU register, and used to process the noisy codeword to determine a candidate version of the transmitted codeword.

Compressing check node unit parameters in low-density parity-check codes in non-volatile memory devices

A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.

Address embedding for encoder and decoder and data processing method thereof

Devices, systems, and methods for improving performance of an iterative decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from an irregular low-density parity-check (LDPC) code, performing, in a first mode of the iterative decoder and on the noisy codeword for a number of iterations, a message passing algorithm between multiple variable nodes and multiple check nodes that represent a parity matrix of the irregular LDPC code, and determining, subsequent to performing the number of iterations, a candidate version of the transmitted codeword. In this first mode, and as part of performing the message passing algorithm, at least one check node of the multiple check nodes is configured to store a portion of multiple check node parameters instead of all of the multiple check node parameters.

Min-sum decoding for irregular low-density parity check codes in memory devices

To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.

Data interleaver for burst error correction

A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node VC message. The method stores, in a check node unit CNU memory, check information associated with the calculated VC message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.

Hybrid precision MS decoder to reduce gate-count for long codes

An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.

Parallel system to calculate low density parity check

Techniques related to improving the error floor performance of a bit flipping (BF) decoder are described. In some examples, error floor performance is improved through determining a set of unreliable check nodes (CNs) and using information about the set of unreliable CNs to compute the flipping energies of variable nodes (VNs). In this manner, the flipping energies can be computed more accurately, thereby lowering the error floor. The set of unreliable CNs can be built through applying various criteria, such as criteria relating to the path length to an unsatisfied CN, the degree of a VN in a path to an unsatisfied CN, and/or checksum value. Path length and VN degree can be applied as selection criteria to determine which CNs qualify as members of the set of unreliable CNs. Checksum value can be applied as a trigger condition for building and/or using the set of unreliable CNs.

Error floor performance of a bit flipping decoder through identifying unreliable check nodes

Devices, systems and methods for improving decoding operations of a decoder are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising N columns, wherein each of at least B columns of the parity matrix has a column weight that exceeds a predetermined column weight, processing the N columns based on a message passing algorithm, and determining, based on the processing, a candidate version of the transmitted codeword, wherein the processing for each of the N columns comprises performing a read operation, a variable node update (VNU) operation, and a check node update (CNU) operation on the first set and the second set, the read operation and the CNU operation on each of the at least B columns spanning two or more time-steps.

Decoding of low-density parity-check codes with high-degree variable nodes

A control of a memory system includes firmware and one error correction code (ECC) module. The module includes a power control engine and ECC components, each ECC component including a power monitor and a power controller. The firmware configures a window of time and a power consumption rate of a select ECC component depending on characteristics of the memory system. The power monitor of the select ECC component measures a power consumption of the select ECC component within the window. The power control engine receives the measurement of power consumption, decides a next power level for the select ECC component, and controls the power controller of the select ECC component such that the select ECC component operates at the next power level.

Power control device and method for error correction code components in memory system

Disclosed are devices, systems and methods improving the convergence of a soft bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of an LDPC code and provided to a communication channel prior to reception by the soft bit-flipping decoder, generating, based on the noisy codeword, one or more messages for passing between a plurality of variable nodes and a plurality of check nodes of the soft bit-flipping decoder, generating a reliability metric for each of the one or more messages, storing the reliability metric only for messages comprising magnitudes that are less than or equal to a predetermined threshold value; and performing, based on the one or more messages and the associated reliability metric for at least one of the one more messages, a single decoding iteration of the soft bit-flipping decoder.

Fast-converging soft bit-flipping decoder for low-density parity-check codes

Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.

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Cupertino, CA, United States of America

Hongwei Duan