International Business Machines Corporation

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Hongwei Dai

Jia Niu

Yang Liu

Peng Ou

Gongqiong Li

Wei Zhang

Xiaofeng Tang

Zhenrong Shi

Jifeng Li

Yu Yun Song

An integrated circuit device includes a plurality of integrated circuit chips located on a common substrate, each respective integrated circuit chip from among the plurality of integrated circuit chips including functional circuitry, a clock generator, clock circuitry including clock terminals at an edge of the respective integrated circuit chip, initial clock conductors configured to conduct a clock signal output by the clock generator from the clock generator to the clock terminals, and functional clock conductors configured to conduct the clock signal from the clock terminals to the functional circuitry. Each respective chip is located on the common substrate in an orientation that exposes the clock terminals on the respective chip to face corresponding clock terminals on at least one other chip among the plurality of integrated circuit chips, configured for interconnection of the plurality of integrated circuit chips into a multi-chip module with a common clock.

Method and apparatus for sharing clocks between separate integrated circuit chips

A computer program product for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

Static timing analysis in circuit design

The present invention discloses a method for simulating a digital circuit comprising: acquiring a gate-level netlist of the digital circuit, the gate-level netlist indicating at least one gate circuit included in the digital circuit and a connection relationship thereof; modifying the netlist, so as to add a timing and power model of each gate circuit, which is used to calculate a time delay generated when a signal inputted to the gate circuit passes through the gate circuit and a power consumed by the gate circuit during its operation; and simulating the digital circuit based on the modified netlist. By adding into the netlist the timing and power model of each gate circuit included in the digital circuit, a power estimation of the digital circuit can be performed while a function verification is performed on the digital circuit, thus function verification is seamlessly combined with the power estimation.

Method and apparatus for simulating a digital circuit

The present invention discloses a method for fixing hold time violations in circuits. The method comprises: creating a topology diagram of the circuit with a branch indicating a signal path where the hold time violation occurs in the circuit, and a node on the branch indicating a port of an element where the hold time violation occurs; dividing the circuit into a plurality of regions; and placing a hold time correction element selectively in a region corresponding to the node in the topology diagram to fix the hold time violation thereof, according to a circuit element density of the region corresponding to the node in the topology diagram. With this method there will be no new element in a region whose circuit element density is excessively large, and it is unnecessary to move an element which has been placed in the circuit and an input/output pin thereof.

Method and apparatus for physical-aware hold violation fixing

A method of for calculating a path delay in static timing analysis (STA) for a circuit design includes determining a connectivity between a first device and a second device in a path of the circuit design, generating a delay constraint associated with the first device and the second device based on the connectivity, the delay constraint specifying a correlation between a first device delay of the first device and a second device delay of the second device, and calculating a path delay of the path based on the first device delay and the second device delay that satisfies the delay constraint.

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Shanghai, China

Hongwei Dai