Inspur Suzhou Intelligent Technology Co., Ltd

Hongtao Man

Tuo Li

Kang Su

Fen Guo

Lang Zhou

An electronic device and a memristor-based logic gate circuit thereof. In the present application, a control end of a controllable switch is connected to a negative end of an output memristor in a MAGIC-based AND logic gate, and whether a second memristor is powered on is controlled by the controllable switch. Thus, when resistance value states of two input memristors in the AND logic gate are different, the controllable switch will conduct and power on the second memristor, and the second memristor will present a low-resistance state at this time. When the resistance value states of the two input memristors are the same, the controllable switch will not conduct and the second memristor will then remain the state unchanged, i.e., presents a high-resistance state. An exclusive OR logic gate is formed by combining the two input memristors and the second memristor.

Electronic device and memristor-based logic gate circuit thereof

The present application discloses a method, a system, a device, and a storage medium for fabricating a GaN chip. The method includes: growing a NbN sacrificial layer on an original substrate, and growing a GaN insertion layer on the NbN sacrificial layer; growing a TaN sacrificial layer on the GaN insertion layer, and growing a semiconductor layer on the TaN sacrificial layer to form a GaN wafer; bonding the GaN wafer with a first surface of a temporary carrier, and removing the NbN sacrificial layer and the TaN sacrificial layer; and transferring remaining material after removal of the NbN sacrificial layer and the TaN sacrificial layer to a target substrate, and removing the temporary carrier from the remaining material to form the GaN chip.

Method for fabricating GaN chip and GaN chip

A parallel bus phase correction method and a device are provided. The method comprises: correcting a data bus, respectively performing phase correction tests on a clock line; determining a first optimal window of the clock line according to the clock test results; correcting the clock line by using a median value of the first optimal window, respectively performing phase correction tests on the data bus according to the multiple second phase adjustment values, and recording corresponding data test results; determining a second optimal window of the data bus according to the data test results; and performing phase correction on normal data transmission on the basis of the median value of the first optimal window and the median value of the second optimal window. The method achieves phase correction and ensures the correctness and accuracy of data transmission, even if a small clock offset is present.

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Suzhou, China

Hongtao Man