Yangtze Memory Technologies Co., Ltd.

HongTao Liu

Yuanyuan Min

Lei Guan

Ying Cui

Shuang Li

Junqiang Xiong

Jichao Huang

Zhongwen Ling

Lijun Teng

Jie Yuan

YaLi Song

WenZhe Wei

Tingze Wang

Junbao Wang

Xiangnan Zhao

Songmin Jiang

A memory, a memory system and a method of operating the memory are disclosed, belonging to the field of storage technologies. When an erase operation is performed on various strings in the block of the memory, if there are a first string that has been erased and a second string that has not been erased among the strings, the selection line coupled to the first selection transistor of the first string is floated in advance before the selection line coupled to the first selection transistor of the second string is floated, to thereby reduce the erasing speed of the first string and prevent the first string from being over-erased during the erasing of the second string, which reduces the possibility of lateral spreading of memory cells in the subsequent first string after programming, and weakens the threshold voltage drift of the memory cells in the first string.

Memory device and methods of erasure operation using different float times for string selection transistors

Disclosed herein are an exemplary memory device and methods for programing the memory device. In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor can be configured to perform a first programming to a memory cell of the memory device with a first step voltage value. The processor is further configured to determine that a step voltage increase condition is met. The processor can also be configured to perform a second programming to the memory cell of the memory device with the second step voltage value. The second step voltage value is greater than the first step voltage value by an incremental voltage value.

Method of reducing program operation time in 3D NAND memory systems

The present disclosure provides a method for erasing a memory device. The method includes applying a word-line voltage to a word line of the memory device, wherein a first set of memory cells coupled to the word line are each configured to store a first number of bits data. The method also includes applying a hold voltage to a selected dummy line for a first time period, wherein a second set of memory cells coupled to the selected dummy line are each configured to store a second number of bits data less than the first number of bits data. The method further includes removing the hold voltage from the selected dummy line after the first time period such that an electric potential of the selected dummy line rises to a first voltage higher than the word-line voltage; and increasing the first time period incrementally in each of subsequent erase loops.

Memory devices, operation method thereof and memory system

In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Method of improving program operation speed in 3D NAND systems

The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Method of reducing Vpass disturb in 3D nand systems

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Hubei, China

HongTao Liu