Samsung Electronics Co., Ltd.

Hongsoo Jeon

Bongsoon Lim

Pansuk Kwak

Seungyeon Kim

Yonghyuk Choi

Daeseok Byeon

Sang-Wan Nam

Sangwan Nam

Sang-Won Park

Sang-won Shim

Chanho Kim

Jaeduk Yu

Jooyong Park

Sujeong Kim

Chaehoon Kim

Jiho Cho

Chung-Ho Yu

Jeunghwan Park

Dong-kil Yun

Homoon Shin

Yoonjee Kim

Yongseok Kwon

A semiconductor device may include stacks extended in a first direction on a substrate, separation structures extended in the first direction and respectively provided between the stacks, vertical channels penetrating each of the stacks, bit lines extended in a second direction crossing the first direction, each of the vertical channels being overlapped with a pair of the bit lines, and contact plugs connecting the bit lines to the vertical channels. Each of the stacks may include electrodes stacked on the substrate and at least two upper separation patterns dividing an upper one of the electrodes into several portions in the second direction. The vertical channels may be classified into a plurality of types, depending on a distance from one of the separation structures in the second direction, and each of the bit lines may be connected to all types of the vertical channels.

Semiconductor device and electronic system therewith

An integrated circuit device includes; a peripheral circuit structure, a cell array structure including gate lines overlapping the peripheral circuit structure and disposed on the peripheral circuit structure in a vertical direction, a conductive plate interposed between the peripheral circuit structure and the cell array structure and including through holes, conductive lines spaced apart from the conductive plate with the cell array structure interposed between the conductive lines and the conductive plate, and through electrodes connected to the conductive lines and extending to the peripheral circuit structure through the cell array structure and the through holes. The through holes include a first through holes arranged along a first straight line extending in a first horizontal direction, and second through holes arranged along a second straight line extending in parallel with the first straight line and spaced apart from the first straight line in a second horizontal direction.

Integrated circuit device with vertical cell array and through electrodes

A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

Memory device including pass transistor circuit

A semiconductor device includes; a first transistor on a substrate and including a first gate electrode, a second transistor on the substrate and including a second gate electrode adjacent to the first gate electrode, an electrode structure including electrodes vertically stacked on the first and second transistors and including first and second pads adjacent to in the first direction, first and second landing pads between the substrate and the electrode structure connected respectively to the first and second landing pads, a first penetration electrode penetrating the electrode structure to connect the first landing pad and the first pad, a second penetration electrode penetrating the electrode structure to connect the second landing pad and the second pad, and lower interconnection lines between the first landing pad and the second landing pad and extending in a second direction substantially perpendicular to the first direction.

Semiconductor device and electronic system including same

A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

A memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines and bitlines, an upper substrate, and a memory cell array. The memory cell array includes a memory blocks. The second semiconductor layer includes a lower substrate, and an address decoder. Each memory block includes a core region including a memory cells, a first extension region adjacent to a first side of the core region and including a plurality of wordline contacts, and a second extension region adjacent to a second side of the core region and including an insulating mold structure. The second extension region includes step zones and at least one flat zone. Through-hole vias penetrating the insulating mold structure are in the flat zone. The wordlines and the address decoder are electrically connected with each other by at least the through-hole vias.

Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same

A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

Memory device having row decoder array architecture

An integrated circuit device includes; a peripheral circuit structure including a peripheral circuit, a first insulating layer covering the peripheral circuit, extension lines in the first insulating layer, and a first bonding pad in the first insulating layer, and a cell array structure including a conductive plate, a memory cell array below the conductive plate, a second insulating layer covering the memory cell array, a second bonding pad in the second insulating layer, a conductive via on the conductive plate, and a line connected to the conductive via. The first bonding pad contacts the second bonding pad, and the integrated circuit device further includes contact plugs electrically connecting the line to the extension lines.

Integrated circuit device including peripheral circuit and cell array structures, and electronic system including same

A nonvolatile memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes word-lines, at least one string selection line, at least one ground selection line, and a memory cell array including at least one memory block. The second semiconductor includes a first address decoder and a second address decoder. The first address decoder is disposed under a first extension region adjacent to a first side of a cell region and includes a plurality of first pass transistors driving the word-lines, the at least one string selection line, and the at least one ground selection line. The second address decoder is disposed under a second extension region adjacent to a second side of the cell region and includes a plurality of second pass transistors driving the at least one string selection line and the at least one ground selection line.

Non-volatile memory device and method of operating nonvolatile memory device

A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

Three-dimensional semiconductor memory device

A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

Memory device

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

Growing community of inventors

Suwon-si, South Korea

Hongsoo Jeon