Samsung Electronics Co., Ltd.

Seoul National University

Hongrak Son

Jaehun Jang

Geunyeong Yu

Youngsik Moon

Youngjun Hwang

Pilsang Yoon

Hanbyeul Na

Changkyu Seol

Dongmin Shin

Bohwan Jun

Wijik Lee

Seonghyeog Choi

Junho Shin

Kangseok Lee

Jiyoup Kim

Jun Jin Kong

Kwanwoo Noh

Hyejeong So

Jung Soo Chung

Hyeonjong Song

Hyunsang Cho

Heeyoul Kwak

Jaehong Kim

Ki-Tae Park

Jongmin Kim

Yong June Kim

Sangyong Yoon

Hwaseok Oh

Jungho Ahn

Jinsoo Lim

Sumin Kim

Chanho Yoon

Seong Hyeog Choi

Hyunseung Han

Daeyeol Yang

Taehyun Song

Mankeun Seo

Yongsung Kil

Soonyoung Kang

Junghyun Hong

Jongyoon Yoon

Sangpyo Kim

A method of transmitting data in a storage device includes encrypting original data based on a homomorphic encryption algorithm to generate encrypted data, generating a parameter for regeneration of a ciphertext higher than an operation level of the encrypted data by using the encrypted data and a key value, and transmitting the encrypted data and the parameter to an external host device.

Storage device, host device and data transfer method thereof

A method of operating a homomorphic encryption operation accelerator includes performing a number theoretic transform (NTT) operation on each of first homomorphic ciphertext and second homomorphic ciphertext, and performing a base conversion operation by adding a partial sum using a first value of the NTT operation.

Homomorphic encryption operation accelerator, and operating method of homomorphic encryption operation accelerator

A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.

ECC decoder and memory controller including the same

A device for supporting a homomorphic encryption operation includes a ciphertext conversion circuit configured to convert first ciphertexts corresponding to a first operation size to second ciphertexts corresponding to a second operation size, different from the first operation size, to convert the operated ciphertext having the second operation size to a third ciphertexts corresponding to the first operation size, and to perform a homomorphic encryption operation on the second ciphertexts.

Device for supporting homomorphic encryption operation and operating method thereof

An Error correction code (ECC) decoder including an input manager configured to sequentially receive a first read data including a plurality of data units read from a plurality of sectors in a memory cell array of a nonvolatile memory device, by unit of sector, a pre-decoder configured to sequentially receive the first read data and generate a respective syndrome of each of the data units, and a main decoder configured to sequentially perform a first ECC decoding on the first read data based on the respective syndrome. The input manager includes a defective sector buffer to store a data unit having a minimum expected error count from among data units on which a first ECC decoding is failed. The main decoder performs a second ECC decoding on a defective data unit stored in the defective sector buffer and receives a second read data from a selected sector corresponding to the defective data unit.

Error correction code decoder, storage controller and storage device

A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

Generalized LDPC encoder, generalized LDPC encoding method and storage device

A homomorphic encryption system includes a homomorphic encryption device encrypting original data into a first ciphertext using a homomorphic encryption algorithm, and a homomorphic encryption operation device receiving the first ciphertext from the homomorphic encryption device and performing an approximate arithmetic operation of a transcendental function with respect to the first ciphertext and a second ciphertext by performing a homomorphic multiplication operation in a binary tree structure.

Homomorphic encryption system for supporting approximate arithmetic operation and method of operating the same

Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.

Error correction circuit using multi-clock and semiconductor device including the same

In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.

Method of error correction code (ECC) decoding and memory system performing the same

Provided are a memory controller calculating an optimal read level, a memory system including the memory controller, and an operating method of the memory controller. The memory controller includes: a processor configured to control a memory operation on the memory device; and a read level calculation module configured to: receive N counting values corresponding to N read levels generated based on a counting operation on data read by using a plurality of read levels, model at least two cell count functions having selected read levels that are selected from the N read levels as inputs, and the N counting values corresponding to the selected read levels as outputs, and calculate an optimal read level based on an optimal cell count function selected from the at least two cell count functions, wherein N is an integer equal to or greater than four, wherein the N counting values include counting values corresponding to at least four different read levels.

Memory controller calculating optimal read level, memory system including the same, and operating method of memory controller

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

Low density parity check decoder and storage device

An encryption device includes: a parameter generating circuit configured to generate an encryption parameter including a number of initial valid bits based on an operation scenario; an encryption circuit configured to generate a cipher text by encrypting a plain text received from the outside, based on the encryption parameter; an operation circuit configured to generate a final cipher text by performing a plurality of operations on the cipher text according to the operation scenario and tag, to the final cipher text, history information of the operations performed on the final cipher text; and a decryption circuit configured to generate a decrypted plain text by decrypting the final cipher text and output a number of reliable bits of the decrypted plain text based on the history information.

Scenario-based encryption device and operating method thereof

A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

Storage controller, storage system and method of operating the same

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

Error correction code engine performing ECC decoding, operation method thereof, and storage device including ECC engine

A client system includes a client-side host device, and a client-side storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control a read operation and a write operation for the storage memory, and a homomorphic encryption and decryption accelerator configured to, based on receiving a read request from the client-side host device, perform homomorphic encryption on first plaintext data that is read from the storage memory, to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client-side host device through the host interface, and based on receiving a write request from the client-side host device, perform homomorphic decryption on second homomorphic ciphertext data that is received through the host interface, to generate second plaintext data, and write the second plaintext data in the storage memory.

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Anyang-si, South Korea

Hongrak Son