Parade Technologies, Ltd.

Integrated Device Technology, Inc.

Hongquan Wang

Ming Qu

Kochung Lee

Zhengyu Yuan

Liang Chang

Liang Xu

Xuexin Ding

Yuanping Chen

Shengyuan Zhang

Mengchuan Gao

Jian Feng Chen

Liang Jie Xu

Qing Li

Yanbo Wang

YingFan Lee

Qing Chen

Jianhong Li

Cindy Cheng

YiTing Chen

Weifeng Zhang

Hongrong Zhang

Baoquan Xu

This application is directed to controlling a low power mode of a data communication channel. An electronic device includes an input interface for receiving an input signal. A signal conditioning circuit is coupled to the input interface, and configured to be disabled and consume power below a first threshold power level in a low power mode. A first signal detector is coupled to the signal conditioning circuit, and a second signal detector is coupled to the first signal detector. The first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit the low power mode. The second signal detector is configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

Exiting of low power modes of redrivers and retimers

This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

Receiver circuit with automatic DC offset cancellation in display port applications

A driver device of a data interface includes an input/output (I/O) interface, a power interface, a transmitter circuit, and a switching unit. The I/O interface is configured to couple to a load device. The power interface is configured to provide a power supply for transmitting data via the I/O interface. The transmitter circuit is coupled to the I/O interface and to the power interface and is configured to be powered by the power supply and provide an output signal to the load device via the I/O interface in a transmitter mode. The switching unit is coupled to the power interface and is configured to switch off the power interface for the transmitter circuit when the transmitter circuit is operating in a low power state. The transmitter circuit has a power consumption level below a threshold power level in the low power state.

Power consumption control for transmitters of retimers in high speed data communication

This application is directed to frequency controlling in an electronic device that includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller identifies a temporal range including a peak instant at which the second reference signal reaches a peak frequency, select a switching instant within the temporal range based on a known temporal position of the peak instant with respect to the temporal range, and control the selector to select the second reference signal as the input signal at the switching instant.

Methods and systems for controlling frequency and phase variations for PLL reference clocks

This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.

Methods and systems for controlling frequency variation for a PLL reference clock

A service redirect operation mode allows a tester device to perform software burn-in, firmware upgrade, and other related device interrogation via a USB Type-C connection. The service redirect operation mode is implemented by modifying a termination state of the configuration channel pins of the USB Type-C receptacle of the device under test. Software and/or hardware executing on the device under test re-configure the resistive arrangement of the configuration channel pins, causing one pin to be connected to a reference voltage via a pull-up resistor and the other pin to be connected to ground via a pull-down resistor. When operating in the service redirect operating mode, two additional signal lines of the USB Type-C receptacles may be used to exchange information between the tester and the device under test using a user-specified interface protocol.

Service redirect over USB Type-C

A source device communicates with a sink device over a main communication channel and configuration data is sent over a display data channel. A retimer is coupled between the source device and the sink device to improve the quality of signal transmitted from the source device to the sink device. The retimer monitors the data being sent on the display data channel to look for a desired command. Once the command is found, a copy of the command is decoded by the retimer and the configuration data and associated values are stored in a storage. The retimer uses the stored configuration data to modify the received communication data signal to match the operational characteristics between the source device and sink device and then transmit the modified signal to the sink device using these operational characteristics.

Display data channel snooping scheme for retimers

A system and a method are disclosed for a hybrid mode re-driver which, among other advantages, reduces power consumption while maintaining signal integrity. Equalization is performed on a signal to remove distortions such as inter-symbol interference. The signal is then analyzed and the quality of the signal is assessed. In some cases, retiming is then performed on the signal to remove additional signal distortions. In other cases, retiming is not performed and is transmitted to a driver while bypassing retiming components. When retiming components are bypassed, the retiming components are placed in a state of reduced power consumption to reduce system power consumption.

Hybrid mode repeater/re-driver for high speed digital video signaling

A system and method are disclosed for level shifting a DDC bus with a low voltage loss. A pull up circuit includes an NMOS transistor, a PMOS transistor and resistor. An NMOS pull up gate is also included in line with the DDC bus. When powered, the level shifter adjusts the voltage of transmitted signals to match the voltage of a receiving device. The resulting adjusted is slightly lower due to a threshold voltage lost across one or more transistors. Additionally, when unpowered, the level shifter releases the signal transmission line. Unadjusted signals can then be transmitted without consumption of power by the level shifter.

Level shifter with low voltage loss

The methods and systems presented herein provide an improved means of correcting the variation of Voltage Output Differential (VOD) in differential drivers. In some embodiments, a high-precision reference voltage is generated not only based on a desired VOD, but also by monitoring the Voltage Common Mode (VCM) in a differential driver. In some embodiments, the VOD is then compared with the high-precision reference voltage to correct the output current. The result is a low-variation output voltage.

Low variation voltage output differential for differential drivers

An input termination circuit includes a first and a second resistor each having a terminal respectively coupled to a first and a second input terminal of the input termination circuit, a first and a second transistor coupled in series between the first resistor and the second resistor, and a third transistor having two terminals respectively coupled to the control circuit and a node between the first and the second transistor. The gate of the third transistor is coupled to ground. The gates of the first and the second transistor are coupled to a control circuit that is adapted to provide a control signal to turn the first and the second transistor on or off.

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Shanghai, China

Hongquan Wang