Huawei Technologies Co., Limited

Via Alliance Semiconductor Co., Ltd.

Future Wei Technologies, Inc.

Hongquan Sun

Wangsheng Xie

Shiqun Gu

Jun Xia

Liming Zhao

Hongying Zhang

Jinghua Zhu

Shuangfu Wang

Hong Tao Liu

Hong Liu

Wei Gao

Minglu Xu

Jiajia Xia

An electrostatic discharge (ESD) protection circuit is provided to minimize ESD damage to an internal circuit in a CDM model. The ESD protection circuit includes two stages of discharging circuits that are coupled to an IO pin and the internal circuit, a first power clamp circuit, and a second power clamp circuit. The first power clamp circuit is electrically connected to a power rail and a ground rail to discharge a part of a current to the ground, and the second power clamp circuit is electrically connected to a second-stage discharging circuit and the ground rail, so that the other part of the current is discharged to the ground through the second power clamp circuit.

ESD protection circuit

This application discloses an integrated circuit, and relates to the field of electronic technologies, to ensure that the integrated circuit has a relatively high bandwidth and can meet an ESD standard. The integrated circuit includes a die and a transmission line coupled to the die. Electrostatic discharge ESD modules are periodically disposed on the transmission line.

Integrated circuit including ESD protection modules

An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.

Merged power pad for improving integrated circuit power delivery

A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a plurality of first resistors and a first selection unit. The first resistors are connected in series with one another and dividing a first operation voltage to generate a plurality of first divided voltages. The first selection unit selects one of the first divided voltages as the first reference voltage according to a first control signal.

Data reception chip

A data reception chip coupled to an external memory including a first input-output pin configured to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and to compare the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage. The voltage generation module includes a first resistor and a second resistor. The second resistor is connected to the first resistor in series. The first and second resistors divide a first operation voltage to generate the first reference voltage.

A control method for a data reception chip. The data reception chip includes a voltage generation module including a plurality of resistors and a selection unit. The resistors are connected in series with one another and divide an operation voltage to generate a plurality of divided voltages. The selection unit selects one of the divided voltages as a reference voltage according to a control signal. The control method includes controlling the selection unit to set the level of the reference voltage to an initial level; receiving data and comparing the data with the reference voltage to generate a compared result; determining whether the compared result is equal to pre-determined data; and directing the selection unit to select another divided voltage when the compared result is not equal to the pre-determined data.

Control method for data reception chip

A data reception chip coupled to an external memory including a first input-output pin to output first data and including a comparison module, a voltage generation module, a logic unit, a detection module and a switching module is provided. The comparison module is coupled to the first input-output pin to configure to receive the first data. The comparison module compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage. The logic unit is coupled to the comparison module and the voltage generation module and outputs at least one switching signal. The detection module detects the logic unit to generate at least one detection signal. The switching module transmits the detection signal to a test pin according to the switching signal.

A data reception chip coupled to an external memory including a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a first resistor, a second resistor, a first capacitor and a second capacitor. The second resistor is serially connected to the first resistor. The first and second resistors divide a first operation voltage to generate the first reference voltage. The second capacitor is serially connected to the first capacitor. The first and second capacitors direct the first reference voltage to track the noise of the first operation voltage.

A low-voltage source bandgap reference voltage circuit is provided. In the circuit, a differential amplification module () is configured to provide negative feedback in a differential input manner, and has one input end connected to a bandgap core module (), and the other input end connected to an output end of a mirror current module () and then connected to the bandgap core module (); the mirror current module () is configured to provide a mirror current for the bandgap core module (); the bandgap core module () is configured to provide a voltage for counteracting positive and negative temperature coefficients; and a starting module () is configured to start the low-voltage source bandgap reference voltage circuit, and has one input end connected to an output end of the differential amplification module (), the other input end connected to a power supply (Vcc), and an output end connected to an output end of the bandgap core module () and then grounded. Therefore, the design of the starting circuit is simplified, the weak current conduction state is effectively prevented, and the startup risk is reduced.

Low-voltage source bandgap reference voltage circuit and integrated circuit

A method for compensating an oscillation frequency, a device, and a phase locked loop (PLL) is applied in the LC oscillating loop, including: sending voltage control signals to one end of a variable capacitor of an LC oscillating loop to generate oscillating signals in the LC oscillating loop through the voltage control signals; obtaining variable bias voltage that reflects changes of external parameters; and sending the variable bias voltage to the other end of the variable capacitor to compensate changes to the oscillation frequency of oscillation signals generated in the LC oscillating loop. This disclosure compensates the changes to the oscillation frequency of the circuit that contains the LC oscillating loop and improves the stability of the circuit oscillation frequency by sending bias voltage to one end of the variable capacitor of the LC oscillating loop.

Method of compensating an oscillation frequency and PLL

A method for compensating an oscillation frequency, a device, and a phase locked loop (PLL) is applied in the LC oscillating loop, including: sending voltage control signals to one end of a variable capacitor of an LC oscillating loop to generate oscillating signals in the LC oscillating loop through the voltage control signals; obtaining variable bias voltage that reflects changes of external parameters; and sending the variable bias voltage to the other end of the variable capacitor to compensate changes to the oscillation frequency of oscillation signals generated in the LC oscillating loop. This invention compensates the changes to the oscillation frequency of the circuit that contains the LC oscillating loop and improves the stability of the circuit oscillation frequency by sending bias voltage to one end of the variable capacitor of the LC oscillating loop.

A phase locked loop (PLL) and a method for charging the PLL are disclosed. The charge circuit includes: a threshold judging module, adapted to output a signal to a receiving module, and when the voltage of a filter reaches a preset threshold, output a valid signal to the receiving module; the receiving module, adapted to receive a trigger signal and output a first control signal to a charging module, and when the signal from the threshold judging module is a valid signal, adapted to output a second control signal to the charging module; the charging module, adapted to charge the filter when receiving the first control signal and stop charging the filter when receiving the second control signal. So that a better voltage may be provided to the PLL to shorten the locking time of the PLL.

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Beijing, China

Hongquan Sun