Applied Micro Circuits Corporation

Smsc Holdings Sarl

Microchip Technology Inc.

Hongming An

Viet Linh Do

CongQing Xiong

Simon Pang

Wei Fu

Bruce H Coy

John Junling Zang

Dixon Chen

Jiachi Yu

Kevin Yang

Shyang Kye Kong

Henry Liang

James Ho

Heng Wang

Mehmet Mustafa Eker

Philip Michael Clovis

Jun Ye

Yanzi Xu

Jim Lew

Christopher T Thomas

Keith Michael Conroy

Allen Carl Merrill

Michael Hellmer

Sudhaker Reddy Anumula

Siqi Fan

Brian Lee Abernathy

Brian Abernethy

Paul Edward Vanderbilt

Congqing Xiong

Howard Chang

Bin Nie

Various embodiments relate to detecting a cable fault within a network. A method may include transmitting a pulse signal to a cable of a shared bus from a node, and observing a signal received at the node in response to the pulse signal. The method may also include determining a fault condition of the cable based on the pulse signal and on an amplitude of each sample of a number of samples of the one or more observed signals.

Diagnosing cable faults within a network

Various embodiments relate to detecting a cable fault within a 10SPE network. A method may include transmitting a pulse signal to a cable of a shared bus from a node, and observing a signal received at the node in response to the pulse signal. The method may also include determining a fault condition of the cable based on the pulse signal and on an amplitude of each sample of a number of samples of the one or more observed signals.

Circuitry of a physical layer for interfacing with a communication bus of a wired local area network is disclosed. The circuitry includes a variable delay driver operably coupled to a communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at the driver output. The circuitry also includes receiver circuitry operably coupled to the communication bus. The circuitry further includes a common mode dimmer operably coupled to the receiver circuitry and the communication bus. The common mode dimmer is configured to protect the receiver circuitry from common mode interference.

Transceiver and driver architecture with low emission and high interference tolerance

An apparatus includes an encoder circuit and a scrambler circuit configured to receive a frame, the frame including a preamble and a payload. The scrambler circuit is further configured to scramble contents of the frame including the payload and at least a portion of the preamble, provide synchronization information with results of scrambling the contents, and send results of scrambling the contents to the encoder circuit.

Scramble of payload and preamble in 10SPE with synchronous and self-synchronous scrambling

In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.

Systems and methods for locking an oscillator to an incoming data signal

Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a reference clock signal generator adapted to provide a reference clock signal. The system also includes a plurality of dividers adapted to divide the reference clock signal using different ratios to provide a plurality of communication port clock signals. The system also includes a plurality of different communication ports adapted to receive the communication port clock signals and adapted to operate in accordance with different communication protocols using the communication port clock signals.

System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios

Various techniques are provided to facilitate a detection system to detect a presence of an externally coupled receiver device, such as a universal serial bus (USB) device. In one example, the system generates a reference current and passes the reference current via a conductor to a shared buffer circuit. The shared buffer circuit is adapted to selectively pass the reference current or a communication signal to the externally coupled receiver device. The system switches between a detect mode where the reference current is provided to the externally coupled receiver device and between a communicate mode where the reference current is blocked and the communication signal is provided to the externally coupled receiver device. The system monitors a voltage value of the conductor and the system monitors a time for the voltage value to reach a pre-determined threshold value in response to the reference current. The system detects a presence of the externally coupled receiver device based on the monitored time.

Detection system and methods

A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q&#x3c;1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value.

Frequency synthesis rational division

Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes generating a common mode voltage signal from the positive portion and the negative portion of the communication signal. The method also includes rectifying the positive portion and the negative portion of the communication signal to provide a rectified signal. The method also includes comparing the common mode voltage, signal with the rectified signal. The method also includes generating a high frequency detect signal in response to the comparing. The method also includes determining whether the communication signal is in an idle state or a high frequency state based on the high frequency detect signal.

High frequency and idle communication signal state detection

Various techniques are provided to detect a state of a communication signal. In one example, a method of detecting a state of a signal includes receiving a differential communication signal comprising a positive portion and a complementary negative portion. The method also includes filtering the positive portion of the communication signal through a first low pass filter to provide a filtered positive portion of the communication signal. The method also includes filtering the negative portion of the communication signal through a second low pass filter to provide a filtered negative portion of the communication signal. The method also includes comparing the filtered positive portion of the communication signal with an internal reference voltage. The method also includes comparing the filtered negative portion of the communication signal with the internal reference voltage. The method also includes generating a low frequency detect signal in response to the comparing operations to indicate whether the communication signal is in a low frequency state.

Low frequency communication signal state detection

A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired.

Auto frequency acquisition maintenance in a clock and data recovery device

A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency.

Frequency hold mechanism in a clock and data recovery device

An integrated circuit (IC) inductor structure is provided with transverse electrical interfaces. The inductor structure is formed on at least one IC circuit layer and has a first axis planar to a circuit layer surface, bisecting the inductor into opposite first and second sides. An input interface is formed on the circuit layer and connected to the inductor first side, parallel to a second axis, which is perpendicular to the first axis. An output interface is formed on the circuit layer and connected to the inductor second side, parallel to the second axis. In one aspect, the inductor has a center tap electrical interface parallel to the axis. In another aspect, the inductor includes a three-dimensional (3D) loop formed over a plurality of the circuit layers.

Integrated circuit inductor with transverse interfaces

Techniques are provided to serialize and delay parallel input data signals and are particularly useful for low power applications. In one example, a device includes a plurality of data input ports adapted to receive N parallel single-ended input data signals, and a clock input port adapted to receive a clock signal substantially synchronized with the parallel single-ended input data signals. The device also includes a cell adapted to serialize the parallel single-ended input data signals to provide N/2 first serial differential output data signals in response to the clock signal, delay the parallel single-ended input data signals, and serialize the delayed parallel single-ended input data signals to provide N/2 delayed second serial differential output data signals in response to the clock signal. The delayed second serial differential output data signals are delayed relative to the first serial differential output data signals. The device also includes a plurality of output ports.

High speed low power cell providing serial differential signals

A system and method are provided for feed-forward equalization (FFE) in a transmission system. The method accepts a serial stream of input digital data signals. For each input data signal, a temporal sequence of signals is generated. Each of the signals in the temporal sequence is selectively shaped. Shaping map include varying the degree of amplification, modifying the slew rate, or varying the time delay. The contributions of the selectively shaped signals in the temporal sequence are then selectively weighted, and a summed output signal is transmitted.

Growing community of inventors

San Diego, CA, United States of America

Hongming An