Micron Technology Incorporated

Intel Corporation

Hongmei Wang

Fabio Pellizzer

Fred D Fishburn

Mingdong Cui

Chandra V Mouli

Luan C Tran

John K Zahurak

Innocenzo Tortorelli

Kurt D Beigel

Karthik Sarpatwari

Rongsheng Yang

Nevil N Gajera

Zengtao T Liu

Amitava Majumdar

Sanjay Rangan

Shawn D Lyonsmith

Ervin T Hill

Rajesh Kamana

Marlon W Hug

Andrea Redaelli

Agostino Pirovano

Zhongze Wang

Robert J Gleixner

Zhongyuan Lu

Richard H Lane

Lorenzo Fratin

Mattia Boniardi

Enrico Varesi

Koushik Banerjee

Christina Papagianni

Lu Liu

Michel Ibrahim Ishac

Luca Crespi

Debayan Mahalanabis

Er-Xuan Ping

Fatma Arzum Simsek-Ege

Casey R Kurth

Kevin R Shea

Hari Giduturi

Janos Fucsko

Lyle D Breiner

Robert J Hanson

Terrence B McDaniel

Shenlin Chen

Brent A McClure

Kathryn H Russo

Andrea Ghetti

Soichi Sugiura

Gitanjali T Ghosh

James L Dale

T Earl Allen

Debra K Gould

Jin Seung Son

Rangan Sanjay

Randall Culver

Irene K Thompson

Jessica M Maderos

Systems, apparatuses, and methods related to medical device data analysis are described. In some examples, a medical device is implanted in a user of the medical device and the data generated by the medical device is not easily accessible to the user. In an example, a controller can be configured to receive, by a mobile device coupled to a medical device, data from the medical device, where the data is a part of a baseline dataset related to the medical device. The controller can be configured to receive different data from the medical device, where the different data is received from the medical device as the different data is generated by the medical device, analyze the data from the medical device and the different data generated by the medical device, and perform an action based on the analyzed data and the different data generated by the medical device.

Medical device data analysis

An apparatus may include a first matrix comprising a first plurality of digit lines, a second matrix comprising a second plurality of digit lines, a plurality of sense amplifiers, and a plurality of selector circuits. Each selector circuit of the plurality of selector circuits may be configured to selectively couple a respective sense amplifier to either a first digit line of the first plurality of digit lines or a second digit line of the second plurality of digit lines.

Memory array architecture having sensing circuitry to drive two matrices for higher array efficiency

Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).

Boost-assisted memory cell selection in a memory array

Methods, systems, and devices for data-based polarity write operations are described. A write command may cause a set of data to be written to a set of memory cells. To write the set of data, a write operation that applies voltages across the memory cells based on a logic state of data to be written to the memory cells may be used. During a first interval of the write operation, a voltage may be applied across a memory cell based on a logic state of a data bit to be written to the memory cell. During a second interval of the write operation, a voltage may be applied across the memory cell based on an amount of charge conducted by the memory cell during the first interval.

Data-based polarity write operations

Methods, systems, and devices for write operation techniques for memory systems are described. In some memory systems, write operations performed on target memory cells of the memory device may disturb logic states stored by one or more adjacent memory cells. Such disturbances may cause reductions in read margins when accessing one or more memory cells, or may cause a loss of data in one or more memory cells. The described techniques may reduce aspects of logic state degradation by supporting operational modes where a host device, a memory device, or both, refrains from writing information to a region of a memory array, or inhibits write commands associated with write operations on a region of a memory array.

Write operation techniques for memory systems

The present disclosure includes systems, apparatuses, and methods related to generating a random data value. For example, a first read operation may be performed on a memory cell programmed to a first state, wherein the first read operation is performed using a first read voltage that is within a predetermined threshold voltage distribution corresponding to the first state. A programming signal may be applied to the memory cell responsive to the first read operation resulting in a snapback event, wherein the programming signal is configured to place the memory cell in a second state. A second read operation may be performed to determine whether the memory cell is in the first state or the second state using a second read voltage that is between the predetermined threshold voltage distribution corresponding to the first state and a second threshold voltage distribution corresponding to the second state.

Random value generator

An example apparatus can include a memory array and control circuitry. The memory array can include a first portion including a first plurality of memory cells. The memory array can further include a second portion including a second plurality of memory cells. The control circuitry can be configured to designate the first portion as active responsive to a determination that the first portion passed a performance test. The control circuitry can be configured to designate the second portion as inactive responsive to a determination that the second portion failed the performance test.

Selective inhibition of memory

Methods, systems, and devices for memory arrays having graded memory stack resistances are described. An apparatus may include a first subset of memory stacks having a first resistance based on a physical and/or electrical distance of the first subset of memory stacks from at least one of a first driver component or a second driver component. The apparatus may include a second subset of memory stacks having a second resistance that is less than the first resistance based on a physical and/or electrical distance of the second subset of memory from at least one of the first driver component or the second driver component.

Memory array with graded memory stack resistances

A memory device having memory cells, voltage drivers, and a controller configured to determine, based on an attribute of a memory cell, whether to apply a drift cancellation pulse that is in the opposite polarity of a programming pulse configured to place the memory cell in a state to represent a bit of data. If the drift in the state of the memory cell from a previous programming operation to write data into the memory cell is predicted to be insufficient to prevent the selection of the memory cell during the application of the programming pulse, the drift cancellation pulse is skipped. Otherwise, the drift cancellation pulse is applied in the opposite polarity of the programming pulse.

Conditional drift cancellation operations in programming memory cells to store data

Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

Discharge current mitigation in a memory array

An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.

Voltage profile for reduction of read disturb in memory cells

Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage&#x2014;a setback voltage&#x2014;of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

Drift mitigation with embedded refresh

Growing community of inventors

Boise, ID, United States of America

Hongmei Wang