Omnivision Technologies, Inc.

Hongli Yang

Xinping James He

Howard E Rhodes

Duli Mao

Yin Qian

Hsin-Chih Tai

Tiejun Dai

Jizhang Shan

Datong Chen

Qingwei Shan

Xiaodong Luo

Hongjun Li

Kimble Dong

Chih-huei Wu

Tai Ching Shyu

James Xinping He

Quingwei Shan

An integrated circuit system includes a first device wafer having a first semiconductor layer proximate to a first metal layer including a first conductor disposed within a first metal layer oxide. A second device wafer having a second semiconductor layer proximate to a second metal layer including a second conductor is disposed within a second metal layer oxide. A frontside of the first device wafer is bonded to a frontside of the second device wafer at a bonding interface. A conductive path couples the first conductor to the second conductor through the bonding interface. A first metal EMI shield is disposed in one of the first metal oxide layer and second metal layer oxide layer. The first EMI shield is included in a metal layer of said one of the first metal oxide layer and the second metal layer oxide layer nearest to the bonding interface.

Integrated circuit stack with integrated electromagnetic interference shielding

An image sensor has an array of photo-sensitive pixels and supports a line-by-line read out of rows. In a normal resolution each row has the same nominal gain and exposure time. In a down-sampling mode the exposure times of the rows are varied according to an alternating sequence having at least two different exposure times. During down-sampling, raw pixel data from rows with different exposure times is combined to simultaneously achieve down-sampling and a high dynamic range.

Image sensor with high dynamic range in down-sampling mode

Embodiments of the present invention are directed to a plurality of light sensor cells disposed in a substrate in a shared pixel arrangement. Common readout circuitry is used to simultaneously read out image information from a group of light sensor cells. The image information from the group of light sensor cells is added together simultaneously and coupled to auto-focus circuitry and/or preview circuitry to provide for better lens adjustments and preview display.

Image sensor with simultaneous auto-focus and image preview

The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. The protective structure has a photodiode contact formed therein to electrically connect the photodiode to the pixel output transistor.

Active pixel having reduced dark current in a CMOS image sensor

A CMOS image sensor that has reduced transistor count is disclosed. The individual pixels are formed by a pinned photodiode and a transfer transistor. An output node receives the signal from the photodiode via the transfer transistor. The output node is shared between multiple pixels. Further, a reset transistor is coupled between a selectable low voltage rail Vor a high voltage reference Vand the output node. The gate of an output transistor is then coupled to the output node. Both the reset transistor and output transistors are shared between multiple pixels.

CMOS image sensor using shared transistors between pixels with dual pinned photodiode

A method of reading out a pixel signal from a pixel is disclosed. The method comprises first capturing a first black reference signal from the pixel prior to the pixel starting an integration period. Next, after completion of the integration period, a pixel signal is captured. Next, a second black reference signal is captured following completion of the integration period. Finally, the first black reference signal, second black reference signal, and pixel signal is output.

Method and apparatus kTC noise cancelling in a linear CMOS image sensor

The image sensor includes a first group and a second group of column readout circuits for reading out pixel signals from said pixels. The total number of column readout circuits in each group is substantially less than the number of columns in the image sensor pixel array. Further included is a multiplexer bus system having selection switches for selectively switching pixel signals from a block of pixels in a column as input into the first group of column readout circuits. The multiplexer bus system also selectively switches pixel signals from another block of pixels in a column as input into a second group of column readout circuits. However, when the first group of column readout circuits is reading and storing said pixel signals, the second group of column readout circuits is transferring out the processed signals. Thus, the first and second groups work alternately.

CMOS image sensor having reduced numbers of column readout circuits

A CMOS camera image sensor that may be combined with additional CMOS camera image sensors to form a multiple-camera security monitoring system. Each CMOS image sensor includes phase-locked loop circuitry. The phase-locked loop circuitry receives a reference input signal and in response thereto synchronizes the video output of the CMOS image sensor to the reference input signal. In one configuration, one of the CMOS image sensors provides the reference signal, while in another configuration, the reference input signal may come from an external circuit. Each CMOS image sensor also includes state selection circuitry. The state selection circuitry allows the video output from the CMOS image sensor to be displayed on,, or all of a display. Thus, the video signals from multiple CMOS image sensors may be displayed on a video monitor simultaneously.

Analog video monitoring system using a plurality of phase locked CMOS image sensors

The present invention is directed to an analog delay line for a color CMOS image sensor which is compatible with MOS fabrication technology. The invention allows for the simultaneous reading of pixel signals from two rows of pixels so that combinations of signals from pixels in different rows may be obtained. The delay line includes a set of storage capacitors on which the pixel signals are stored, and a means for writing the signals from the pixels onto the capacitors in sequence. The stored analog pixel signals may then be read out from the delay line at the appropriate time so that they may be combined with pixel signals from adjacent pixels in different rows. In one embodiment, two delay lines are used, so that pixel signals from a current row can be written into one delay line, while the pixel signals from a previous row are being read out from the other delay line. In another embodiment, a single delay line is used in combination with a single pixel delay circuit. When the single pixel delay circuit is used, the pixel signals from a previous row are read out from the delay line and temporarily stored in the single pixel delay circuit, one at a time, shortly after which the pixel signals from the next row are written into the delay line. The pixel signals from the single pixel delay circuit are then read out at the same time that the pixel signals from the next row are being read in, so that signals from adjacent pixels in adjacent rows are available to the processing circuitry at the same time.

CMOS sensor having analog delay line for image processing

In the field of imaging, various components may contribute to a loss in resolution at higher spatial frequencies, both horizontally and vertically. Higher spatial frequencies may occur at the edge of an image, where there may be a large transition in the signal output between adjacent pixels. To compensate, an edge enhancement method that produces overshoots in the transitions of the video image signal is used. One of the problems with the edge enhancement method is that the noise in the input signal may not be adequately suppressed. To suppress the background noise in the video image signal while still performing the desired edge enhancement function, biasing circuitry may be used to suppress the smaller transitions in the input signal. In particular, the biasing circuitry may be placed in the signal path between the output of a first delay line and the noninverting inputs of two of the signal amplifiers. In this manner, the smaller transitions in the signal which represent background noise may be suppressed, while the edges of the video image signal are still enhanced.

Edge enhancement with background noise suppression in video image processing

An analog median filter for rejecting isolated impulse noise while preserving signal step changes in image processing. The analog median filter includes a number of transconductance amplifiers with additional CMOS inverters coupled to the outputs of the amplifiers. The outputs of the inverters are coupled together in a feedback loop configuration with the amplifiers. The CMOS inverters act as a type of additional current source for the amplifiers, so as to sharpen the corners of the transfer curve at various current levels. The low gain of the inverters improve the stability of the output range. Because inverters are used, the feedback loop is coupled to the noninverting inputs of the amplifiers, while the input signals are coupled to the inverting inputs of the amplifiers.

Analog median filter circuit for image processing

An image acquisition and processing system that can eliminate or reduce the effects of offset voltage and threshold voltage is disclosed. The system contains a plurality of operational amplifiers each is used in an integrator. Each of the operational amplifiers has an offset voltage. The output of the integrator is sampled twice by a dual sampling circuit, one when connected to a photo-sensor and the other when not connected to the photo-sensor. The difference between the two samplings cancels out the effect of the offset voltage. The system also contains a plurality of transistors used as source follower. Each of the transistors is connected to an output terminal of the dual sampling circuit. These transistors have different threshold voltages. The output of a transistor is sampled. A predetermined voltage is then applied to the transistor and the output is again sampled. The difference between these two samples cancels out the effect of the threshold voltage. The effect of the predetermined voltage can be canceled out by taking a second difference between the twice sampled output originated from two transistors.

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Cupertino, CA, United States of America

Hongli Yang