Intel Corporation

Hongjiang Song

Yan W Song

Zhiguo Qian

Zhichao Zhang

Malcolm Harold Smith

Yueming He

Mingming Xu

Chunyu Zhang

Kevin E Arendt

Mohit Verma

Girish P Ramanathan

Mahender R Voruganti

Pankaj Dudulwar

Dianbo Le

Tofayel Ahmed

An apparatus is described having an electrical interface that supports a first specification and a second specification. The first specification specifies differentially transmitted data. The second specification specifies at least three transmitted data signals. The electrical interface includes a plurality of modular transmitter circuits where each transmitter circuit includes a single ended driver and a select circuit. The select circuit is to select either one end of a differential signal associated with the first specification or one of the at least three transmitted data signals associated with the second specification.

Multi-standard single interface with reduced I/O count

Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.

Clock recovery circuit and method of operating same

Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a circuit structure that can be configured to operate in either the C-PHY mode or the D-PHY mode of the MIPI specification. In one device, the circuit structure can be included in a receiver of the device and configured to operate in the C-PHY mode. In another device, the circuit structure can be included in a receiver of the device and configured to operate in the D-PHY mode.

Reconfigurable camera serial interface

Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

Low voltage transmitter with variable output swing

Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

Smart impedance matching for high-speed I/O

Embodiments include apparatuses, methods, and systems for transmitting a data signal over one or more transmission lines. In one embodiment, a transmitter circuit includes a plurality of programmable impedance driver (PID) circuits coupled in parallel with one another to drive a data signal on a transmission line. The individual PID circuits may include a pull-up transistor to receive a pull-up signal, a pull-down transistor to receive a pull-down signal, and first and second resistors coupled in series with one another between the pull-up and pull-down transistors. An output contact may be coupled to a node between the first and second resistors to pass an output signal that is responsive to the pull-up and pull-down signals. The individual PID circuits may further include a switch transistor coupled in parallel with the first and second resistors, and a control contact coupled to the switch transistor to receive a control signal to switch the switch transistor on or off to control an impedance at the output contact.

Programmable impedance transmitter for serial communication

Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal.

Low power squelch circuit

Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Low power digital phase interpolator

In one embodiment, an apparatus includes a clock generator to generate differential clock signals. The apparatus also includes a distributed polyphase filter to obtain phase-corrected multi-phase clock signals based on the differential clock signals.

Distributed polyphase filter

Described herein is a low power high-speed digital receiver. The apparatus of the receiver comprises: a sampling unit operable to sample a differential input signal and to boost input signal gain, the sampling unit to generate a sampled differential signal with boosted input signal gain; and a differential amplifier to amplify the sampled differential signal with boosted input signal gain, the differential amplifier to generate a differential amplified signal.

Low power high-speed digital receiver

In one embodiment, an apparatus includes a power switch to provide a local power voltage at least one gated circuit based on a control signal. The apparatus also includes a delay sensor to provide a delay substantially equivalent to a processing delay of the at least one gated circuit. The apparatus also includes a phase detector to provide the control signal based at least in part on the delay.

Adaptive power gating and regulation

Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

Clock repeater and phase-error correcting circuit

Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data when the phase between the incoming data and the receiver clock varies relatively slowly. Embodiments comprise a fast tracking loop performs to track the data when the phase between the incoming data and the receiver clock varies rapidly. The fine tracking loop adjusts the phase of a receiver clock to track the data eye of the data. The fast tracking loop over-samples the data and then chooses the sample that best represents the data. In some embodiments, the data recovery circuit can switch between receiving data from the fine tracking loop and receiving data from the fast tracking loop.

Systems and methods for data recovery in an input circuit receiving digital data at a high rate

A method and apparatus, in some embodiments the apparatus includes a sampler, using a plurality of sampling clocks, to sample a first set of data of an incoming data signal to determine a first phase shift indicator and to sample a second set of data of the incoming data signal to determine a second phase shift indicator, a data recovery circuit (DRC) including control logic to determine a phase control signal based on the first and the second phase shift indicators, and a phase interpolator to receive the phase control signal and adjust a phase of the sampling clocks, wherein the phase interpolator provides the plurality of sampling clocks.

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Chandler, AZ, United States of America

Hongjiang Song