Google Inc.

Wisconsin Alumni Research Foundation

Hongil Yoon

Jason Rupert Redgrave

Manu Gulati

Albert Meixner

Benjamin K Dodge

Gurindar Singh Sohi

Keith Robert Pflederer

Allan Douglas Knies

Vinod Chamarty

Xiaoyu Ma

Rahul Jagdish Thakur

Weiping Liao

Gurindar S Sohi

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

A computer architecture provides a memory cache that is accessed not by physical addresses but by virtual addresses directly from running processes. Ambiguities that can result from multiple virtual addresses mapping to a single physical address are handled by dynamically tracking synonyms and connecting a limited number of virtual synonyms mapping to the same physical address to a single key virtual address that is used exclusively for cache access.

Cache accessed using virtual addresses

A computer cache system delays cache coherence invalidation messages related to cache lines of a common memory region to collect these messages into a combined message that can be transmitted more efficiently. This delay may be coordinated with a detection of whether the processor is executing a data-race free portion of the program so that the delay system may be used for a variety of types of programs which may have data-race and data-race free sections.

Computer cache system providing multi-line invalidation messages

Growing community of inventors

San Jose, CA, United States of America

Hongil Yoon