Skhynix Inc.

Yonsei University

Hongil Yoon

Kangwook Jo

Eui-Young Chung

Jeongbin Kim

Jongil Hong

KiTae Kim

Seungjin Lee

Taehee You

Kyungseon Cho

Daehyung Cho

Minyoung Im

Sachin Pathak

A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.

Method for designing an FPGA

A magnetic memory device includes a magnetic element and a write circuit electrically connected to two nodes of the magnetic element and configured to provide a write current to the magnetic element, wherein the write current includes a first current having a first peak applied for a first time period and a second current having a second peak applied for a second time period, where the second peak is smaller than the first peak and the second period is longer than the first time period.

Magnetic memory device with enhanced write performance and operation method thereof

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Technology mapping method of an FPGA

A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

Look up table including a nonvolatile memory element, FPGA including the look up table, and method for designing the FPGA

A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.

Look up table including magnetic element, FPGA including the look up table, and technology mapping method of the FPGA

An operating method of a magnetic memory device may include: a first step of retrieving write data to be written to a plurality of magnetic memory cells sharing a bit line according to a write request, the write data including more of a first type of data than a second type of data; a second step of writing the first type of data simultaneously to all cells of the plurality of magnetic memory cells; and a third step of writing the second type of data to a portion of the plurality of magnetic memory cells, the second type of data being different from the first type of data.

Operating method of a magnetic memory device

A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each including a magnetic resistance element and a switching element coupled in series to the magnetic resistance element and switched by a word line signal, a dummy cell coupled to the bit line, and a spin-hall effect material layer between the bit line and the magnetic resistance element. The magnetic resistance element may write data according to a first current that flows through the dummy cell and flows in a direction parallel to the magnetic resistance element, and a second current that flows through the magnetic resistance element.

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Seoul, South Korea

Hongil Yoon