Huawei Technologies Co., Limited

Honghui Yuan

Heng Liao

Hu Liu

Hou Fun Lam

Jiajin Tu

Fan Zhu

Bin Xu

Bing Li

Xianbo Chen

Binbin Yao

Luping Cui

Zhanying He

A data processing circuit is disclosed. The data processing circuit relates to the field of digital circuits, and includes a first computing circuit and an input control circuit. The first computing circuit includes one or more computing sub-circuits. Each computing sub-circuit includes a first addition operation circuit, a multiplication operation circuit, a first comparison operation circuit, and a first nonlinear operation circuit. The first nonlinear operation circuit includes at least one of an exponential operation circuit and a logarithmic operation circuit. The input control circuit is configured to: control the first computing circuit to read input data and an input parameter, and control, according to a received first instruction, the operation circuit in the computing sub-circuit included in the first computing circuit, to perform an operation on the input data and the input parameter.

Data processing circuit for neural network

Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Matrix multiplier

A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jgroup of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jgroup of proposal region sequence and determine a suppression vector of the jgroup of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.

Data processing method and apparatus

A data processing method is disclosed, the method includes: receiving a request message that is sent from a host service layer and transparently transmitted through a host driver layer, where the request message includes at least one acceleration type identifier and to-be-acceleratedly-processed service data, and each acceleration type identifier corresponds to one type of accelerated processing; and performing at least one type of accelerated processing in a one-to-one correspondence with the at least one acceleration type identifier on the service data. In the method, interaction between the host service layer and the hardware processing unit does not need coordination of a specialized driver, so that dependence on a specific underlying driver for a service layer may be shielded.

Growing community of inventors

Hangzhou, China

Honghui Yuan