Chinese Academy of Sciences

Vmware, Inc.

Honggang Liu

Bing Jiang Sun

Shengkai Wang

Hudong Chang

Donghai Han

Chao Zhao

Huaxiang Yin

Dapeng Chen

Jun Luo

Qi Wu

Lele Zhang

Kejia Cui

Example methods and systems for media access control (MAC) address assignment for virtual network interface cards (VNICs) are described. One example may involve a first computer system may determining a first MAC address portion that is uniquely associated with the first computer system. A first VNIC may be assigned with a first MAC address that includes (a) the first MAC address portion and (b) a third MAC address portion that is uniquely associated with the first VNIC on the first computer system. A second VNIC may be assigned with a second MAC address that includes (a) the first MAC address portion and (b) a fourth MAC address portion that is uniquely associated with the second VNIC on the first computer system. The first computer system may perform traffic handling by processing packets specifying the first MAC address or the second MAC address.

Media access control (MAC) address assignment for virtual network interface cards (VNICS)

The present disclosure relates to the field of semiconductor Integrated Circuit (IC) manufacture, and provides an InGaAs-based double-gate PMOS Field Effect Transistor (FET). The FET includes a bottom gate electrode, a bottom gate dielectric layer, a bottom gate interface control layer, an InGaAs channel layer, an upper interface control layer, a highly doped P-type GaAs layer, an ohmic contact layer, source/drain metal electrodes, a top gate dielectric layer and a top gate electrode. The source/drain metal electrodes are located on opposite sides of the ohmic contact layer. A gate trench structure is etched to an upper surface of the interface control layer between the source and drain metal electrodes. The top gate dielectric layer uniformly covers an inner surface of the gate trench structure, and the top gate electrode is provided on the top gate dielectric layer. The present disclosure provides a PMOS FET with better gate control functionality and a low interface density with the double-gate structure and interface control layer design, in order to meet the requirements of high-performance PMOS transistors.

Dual-gate PMOS field effect transistor with InGaAs channel

The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlYOinterface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlYOinterface passivation layer, wherein 1.2&#x2264;x&#x2264;1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlYOinterface passivation layer, changes the average number of atomic coordination in the AlYOinterface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlYOinterface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

Composite gate dielectric layer applied to group III-V substrate and method for manufacturing the same

A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Semiconductor device and manufacturing method thereof

Growing community of inventors

Beijing, China

Honggang Liu