Winbond Electronics Corporation

Windbond Electronics Corp.

Windbond Eelctronics Corp.

Hongchin Lin

Shyh-Chyi Wong

Kai-Hsun Chang

Chien-Zhi Chen

Chein-Zhi Chen

Chia-Hsiang Sha

A current-mode identifying circuit includes a current duplicating circuit for duplicating a cell current, which flows through a selected flash cell in a multilevel flash memory, and for outputting multiple duplicate cell currents. Each of multiple reference current generating units draws a predetermined reference current from a respective duplicate cell current to form a difference current. Each of multiple current comparators receives the difference current from a corresponding reference current generating unit, and outputs a logic signal corresponding to magnitude of the difference current. An encoder encodes the logic signals from the current comparators to identify a level associated with the cell current.

Current-mode identifying circuit for multilevel flash memories

The present invention relates to a charge-pumping circuit for low-supply voltage. A small charge-pumping circuit was added at the gates of the original Dickson charge-pumping circuit's each stage for bias voltage and the first transistor group was added between well and gate. The second transistor group was added between the gate and drain of original transistor. Thus, the charge-pumping circuit for low-supply voltage can supply a higher positive or negative voltage.

Charge-pumping circuits for a low-supply voltage

A SOI device structure is formed on a SOI substrate having a body contact. The SOI substrate has an insulating layer thereon and a silicon layer is disposed on the insulating layer. A gate is disposed on the silicon layer. A source region and a drain region are respectively disposed within the silicon layer beside the gate. A body contact is provided at an interface between the insulating layer and the silicon layer wherein the body contact is preferably located between the source region and the gate. The body contact, disposed between the source region and the gate can reduce kink effect and body effect, thereby enhancing the performance of device formed on SOI.

Soi structure with a body contact

A circuit and a method for measuring the read operation delay on DRAM bit lines are disclosed. The circuit comprises a plurality of circuit blocks connected in series, each having a 1-bit DRAM cell. The output of the DRAM cell in each circuit block is connected to the word line of the DRAM cell of the next circuit block through inverters, so the read operation in the DRAM cell of the next circuit block is triggered. The total delay between the word line at the first circuit block and the output of the last circuit block can be measured on the oscilloscope. The delay for every 1-bit DRAM cell is equal to the total delay divided by the number of circuit blocks.

Method and circuit for measuring the read operation delay on DRAM bit

A semiconductor integrated circuit includes a first charge pumping circuit connected to an input node. The first charge pump circuit includes a plurality of first driving transistors and charges an input voltage at the input node to a control voltage. A second charge pumping circuit includes a plurality of second driving transistors that each receive the control voltage from the first charge pump. The received control voltage controls the driving of the second transistors when charging an output node to an output voltage. To eliminate body effects, the semiconductor integrated circuit further includes a plurality of body transistors that connect the source and body terminals of the driving transistors.

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Taipei, Taiwan

Hongchin Lin