Synopsys, Inc.

Tela Innovations, Inc.

Aprio Technologies, Inc.

Hongbo Tang

Wai-Yan Ho

Shao-Po Wu

Xin Wang

Meg Hung

Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.

Intermediate layout for resolution enhancement in semiconductor fabrication

The present invention relates to a method for efficiently performing hierarchical design rules checks (DRC) and layout versus schematic comparison (LVS) on layout areas of an integrated circuit where cells overlap or where a cell and local geometry overlap. With the present invention, a hierarchical tree describes the integrated circuit's layout data including cells having parent-child relationships and including local geometry. The present invention performs efficient layout verification by performing LVS and DRC checking on the new portions of an integrated circuit design and layout areas containing overlapping cells. When instances of cells overlap, the present invention determines the overlap area using predefined data structures that divide each cell into an array of spatial bins. Each bin of a parent is examined to determine if two or more cell instances reside therein or if a cell instance and local geometry reside therein. Once overlap is detected, the areas of the layout data corresponding to the overlap areas are selectively flattened prior to proceeding to DRC and LVS processing. During selective flattening of the overlap areas, the hierarchical tree is traversed from the top cell down through intermediate nodes to the leaf nodes. Each time geometry data is located during the traversal, it is pushes directly to the top cell without being stored in intermediate locations. This provides an effective mechanism for selective flattening.

Layout overlap detection with selective flattening in computer

A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design language (e.g., HDL or VHDL) description of the integrated circuit can be translated by a computer system into a netlist of technology specific gates and interconnections there between. The cells of the netlist are then placed spatially in an integrated circuit layout and the connections between the cells are routed using computerized place and route processes. Circuit designers next run layout verification tests on the layout to verify that the geometry and connectivity data of the design meets specific design rules and matches logically with the schematic representation. The present invention provides a method of layout verification where unchanged subdesigns of a hierarchical IC design can be reused upon subsequent verification processes of the same IC design. They are reused for both design rule checking (DRC) and layout versus schematic (LVS) comparison. By reusing some of the subcell designs, subsequent verification processes of the present invention can be performed very efficiently. To account for faults attributed to subcell interfaces, the present invention advantageously determines subcell overlap areas within the layout and selectively flattens and verifies these areas in addition to any subcell designs that were not previously validated. Further, the invention determines updated connectivity information for new subcell designs.

Method and system for layout verification of an integrated circuit

Selective flattening in layout areas in computer implemented integrated

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Hongbo Tang