Intel Corporation

Hongbo Rong

Youfeng Wu

Hyunchul Park

Cheng C Wang

Todd A Anderson

Tatiana Shpeisman

Victor W Lee

Jong Soo Park

Mikhail Smelyanskiy

Jaewoong Chung

Gilles A Pokam

Arch D Robison

Paul M Petersen

Geoff Lowney

Peng Tu

Xipeng Shen

Jongsoo Park

Hai Liu

P G Lowney

Cheng Wang

A method for designing a system on a target device includes generating an intermediate representation of the system from a functional specification of a high-level description of a system. From the high-level description of the system, one or more directives are identified that (1) transform a portion of the system with a specific technique, (2) build a spatial layout for the system by dividing the system according to functionalities, and (3) specialize the system in response to the spatial layout. The intermediate representation of the system is modified in response to the one or more directives.

Method and apparatus for supporting programmatic control of a compiler for generating high-performance spatial hardware

Technologies for automatic reordering of sparse matrices include a computing device to determine a distributivity of an expression defined in a code region of a program code. The expression is determined to be distributive if semantics of the expression are unaffected by a reordering of an input/output of the expression. The computing device performs inter-dependent array analysis on the expression to determine one or more clusters of inter-dependent arrays of the expression, wherein each array of a cluster of the one or more clusters is inter-dependent on each other array of the cluster, and performs bi-directional data flow analysis on the code region by iterative backward and forward propagation of reorderable arrays through expressions in the code region based on the one or more clusters of the inter-dependent arrays. The backward propagation is based on a backward transfer function and the forward propagation is based on a forward transfer function.

Technologies for automatic reordering of sparse matrices

Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.

Conjugate code generation for efficient dynamic optimizations

Technologies for optimizing sparse matrix code include a target computing device having a processor and a field-programmable gate array (FPGA). A compiler identifies a performance-critical loop in a sparse matrix source code and generates optimized executable code, including processor code and FPGA code. The target computing device executes the optimized executable code, using the processor for the processor code and the FPGA for the FPGA code. The processor executes a first iteration of the loop, generates reusable optimization data in response to executing the first iteration, and stores the reusable optimization data in a shared memory. The FPGA accesses the optimization data in the shared memory, executes additional iterations of the loop, and optimizes the additional iterations of the loop based on the optimization data. The optimization data may include, for example, loop-invariant data, reordered data, or alternate data storage representations. Other embodiments are described and claimed.

Technologies for optimizing sparse matrix code with field-programmable gate arrays

Technologies for persistent memory programming include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may assign a virtual memory address of a target location in persistent memory to a persistent memory pointer using persistent pointer strategy, and may dereference the pointer using the same strategy. Persistent pointer strategies include off-holder, ID-in-value, optimistic rectification, and pessimistic rectification. The computing device may log changes to persistent memory during the execution of a data consistency section, and commit changes to the persistent memory when the last data consistency section ends. Data consistency sections may be grouped by log group identifier. Using type metadata stored in the nonvolatile region, the computing device may identify the type of a root object within the nonvolatile region and then recursively identify the type of all objects referenced by the root object. Other embodiments are described and claimed.

Technologies for persistent memory programming

Methods, apparatus, systems and articles of manufacture are disclosed to optimize sparse matrix execution. An example disclosed apparatus includes a context former to identify a matrix function call from a matrix function library, the matrix function call associated with a sparse matrix, a pattern matcher to identify an operational pattern associated with the matrix function call, and a code generator to associate a function data structure with the matrix function call exhibiting the operational pattern, the function data structure stored external to the matrix function library, and facilitate a runtime link between the function data structure and the matrix function call.

Methods, systems and apparatus to optimize sparse matrix applications

Logic and instruction to monitor loop trip count are disclosed. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.

Instruction and logic to monitor loop trip count and remove loop optimizations

Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

Technologies for low-level composable high performance computing libraries

In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.

Co-designed dynamic language accelerator for a processor

In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.

Allocation of alias registers in a pipelined schedule

Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.

Software pipelining at runtime

In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

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San Jose, CA, United States of America

Hongbo Rong