Marvell International Limited

Marvell Asia Pte., Ltd.

Marvellworld Trade Ltd.

Hong Yu Chou

Donald Robert Pannell

Dance Wu

Ramya Krishna Devineni

Samuel Kong

Chuanhai Zhou

Christopher Mash

Daryl Hoot

Weiwen Zhu

Lian Xie

Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.

Packet processing system with energy saving features

A network switch includes a plurality of ports for communicating over a network. Processing circuitry processes inbound frames received from the network via the ports and sends outbound frames to the network. Remote management circuitry (RMU) is responsive to commands received from a host device external to the network switch. The RMU receives via one of the ports a remote access request frame from the host device, wherein at least part of the remote access request frame is encrypted, and decrypts the remote access request frame. In response to successful decryption of the part of the remote access request frame, the RMU accesses one or more configuration registers of the network switch in accordance with the remote access request frame, composes a remote access response frame, at least a portion of the remote access response frame being encrypted, and sends the remote access response frame to the host device.

Trusted remote management unit

An Ethernet communication device includes a data interface and circuitry. The data interface is configured for communicating with a neighbor device. The circuitry is configured to exchange Ethernet data frames with the neighbor device over the data interface, wherein successive data frames are separated in time by an Inter-Packet Gap (IPG) having at least a predefined minimal duration, and to further exchange with the neighbor device, over the data interface, during the IPG between Ethernet frames exchanged on the data interface, a wake-up/sleep command that instructs switching between an active mode and a sleep mode.

Ethernet PHY-MAC communication with in-band wake-up/sleep commands

A first serial management interface device includes one or more input/output pins and a controller coupled to the one or more input/output pins. The controller receives a first frame from a second serial management interface device via a first input/output pin and generates a first error code based on the first frame received from the second serial management interface device. The controller receives a second frame from the second serial management interface device via a second input/output pin subsequent to receiving the first frame. The second frame includes a second error code. The controller compares the first error code to the second error code to determine whether first error code and the second error code match.

Serial management interface with improved reliability

A first serial management interface device includes an input/output pin, a register, and a controller. The controller is configured to send a first frame to a second serial management interface device via the input/output pin. The controller is configured to generate an error code based on the first frame sent to the second serial management interface device. The controller is configured to store the error code in the register to send to the second serial management interface device.

Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a central processing unit (CPU) that performs routing related processing on packets prior to sending the packets to one or more destination devices and a switch configured to send packets to the CPU. The switch is configured to, in response to receiving a new packet for the CPU, determine whether a wake-on-frame mechanism is enabled. When the wake-on-frame mechanism is enabled, the switch causes an interrupt signal to be sent to the CPU, such that receiving the interrupt signal will cause the CPU to wake up. When the wake-on-frame mechanism is disabled, the switch sends the packet to the CPU.

Wake-on-frame for frame processing devices

A physical layer circuit includes registers and a timing circuit. The registers are configured to store a future time of day, a local hardware time and a compensation value. The timing circuit is configured to: determine a relationship between the local hardware time and a grandmaster time; select the future time of day; determine a difference between a local clock and a grandmaster clock and set the compensation value equal to the difference; subsequent to determining the difference, enable maintenance of a current time of day; when the local hardware time matches the future time of day, begin updating the current time of day based on the compensation value to match the grandmaster time; and adjust the compensation value to compensate for drift between the current time of day and the grandmaster time.

Maintaining a time of day in a physical layer circuit including compensating for drift away from a grandmaster time

A serial management interface master device includes an input/output pin and a controller including an error code calculator. The controller is configured to output a first access frame on the input/output pin to cause data to be written to a first register of a serial management interface slave device connected to the input/output pin; cause the error code calculator to generate first error code bits based on the first access frame sent to the serial management interface slave device; and output a second access frame including the first error code bits to the serial management interface slave device on the input/output pin to cause the first error code bits to be written to a second register of the serial management interface slave device.

A switching device is provided and includes a processor and a physical layer device. The processor is configured to generate a synchronization frame and a corresponding follow up frame. The follow up frame is generated while or subsequent to the generating of the synchronization frame and without waiting for an egress timestamp indicating when the synchronization frame is to be transmitted from the switching device to a network device. The physical layer device is configured to: receive the synchronization and follow up frames from the processor; prior to transmitting the follow up frame to the network device, modify the follow up frame to include the egress timestamp indicating when the synchronization frame is transmitted from the switching device via the physical layer device; and perform a precision time protocol process including transmitting the synchronization and follow up frames from the switching device to the network device for clock synchronization.

Bridges including physical layer devices for indicating transmission times of synchronization frames by modifying previously generated corresponding follow up frames

A network device operative to maintain a first time of day (ToD) synchronized to a grandmaster clock is provided and includes a physical layer (PHY) circuit and a processor. The PHY circuit: maintains the first ToD in a first format and a second ToD in a second format; initially sets the second ToD based on a master ToD of the grandmaster clock; and updates the second ToD to maintain synchrony with a master time of the grandmaster clock by incrementing a counter based on a local clock, periodically updating the first ToD responsively to a counter value of the counter, and based on the updated first ToD and a compensation value, periodically adjusting the second ToD to more closely match the master time. The processor ascertains whether the second ToD has drifted from the master time and adjusts the compensation value based on whether the second ToD has drifted.

Maintaining a time of day in physical layer circuit of a network device while periodically compensating for drift away from a master time of a grandmaster clock

A network device is provided and includes a physical layer module and a control port. The physical layer module includes one or more ports, which: receives and alters a first synchronization frame to include a timestamp indicating a received time. The control port: receives the first synchronization frame from the one or more ports; provides the first synchronization frame to a control module; and receives, from the control module a second synchronization frame including the timestamp and a follow up frame corresponding to the second synchronization frame. The one or more ports: receives the second synchronization and follow up frames from the control port and transmits the received frames from the network device; and generates an egress timestamp for the second synchronization frame and updates a timestamp field of the follow up frame or calculates a residence time and updates a correction field of the follow up frame.

Systems and methods for indicating when frames egress a PHY module of a network device

A network device including a port having register and timing modules. The register module includes first ToD, loadpoint, and compensation registers. The timing module includes a second ToD register and ToD module and operates based on a local clock signal. The register module receives a ToD from a control module, which is separate from the network device and selects an initial hardware time. The ToD is a future time and is based on a grandmaster clock signal. The first ToD and loadpoint registers store the ToD and initial hardware time. The compensation register stores a compensation value from the control module and determined based on a difference between local and grandmaster clock signals. The ToD module, when local and initial hardware times match: transfers the ToD between first and second ToD registers; and updates the ToD in the second ToD register based on the local clock signal and compensation value.

System and method for maintaining a time of day in a port of a PHY module

Embodiments include a method for operating a network switch that is coupled to a plurality of devices, the method comprising: determining whether the network switch has, for at least a threshold period of time, (i) not received any data packets from the plurality of devices and (ii) not transmitted any data packets to the plurality of devices; in response to determining that the network switch has, for at least the threshold period of time, (i) not received any data packets from the plurality of devices and (ii) not transmitted any data packets to the plurality of devices, entering, by the network switch, a first mode of operation; while the network switch operates in the first mode of operation, monitoring a plurality of signals; and in response to detecting a change in one of the plurality of signals, exiting, by the network switch, the first mode of operation.

Growing community of inventors

Saratoga, CA, United States of America

Hong Yu Chou