Marvell Asia Pte., Ltd.

Marvell International Limited

Hong Xue

Yihui Li

Hui Wang

Xin Ma

Fei Guo

Yonghua Song

Tao Shui

Hao Zhou

Jianmin Guo

A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.

Systems and methods for calibrating impedance of a low power voltage-mode transmitter driver

Systems for calibrating impedances caused by a first component and a second component of a voltage-mode transmitter driver are described herein. The first component includes a first transistor and a first resistor connected to the first transistor, wherein the first component is connected to a voltage source and an output end of the voltage-mode transmitter driver, respectively. The second component includes a second transistor and a second resistor connected to the second transistor, wherein the second component is connected to the output end of the voltage-mode transmitter driver, and a third transistor, respectively. A first gate of the third transistor is applied with a first tunable gate voltage, and the first tunable gate voltage is configured to be tuned to calibrate a first impedance between the output end and a ground to match with a second impedance between the voltage source and the output end.

A phase-locked loop (PLL) with a decreased frequency tuning gain Kand a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, K, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/&#x3b2; of that of the second voltage to current converter, wherein &#x3b2;&#x3e;1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is &#x3b1; times of the main charge pump, the capacitance of C1 may be reduced to just (1&#x2212;&#x3b1;) times of what it needed in a conventional loop stability compensation method, wherein &#x3b1;&#x3c;1.

Low-jitter phase-locked loop

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Shanghai, China

Hong Xue