Industrial Technology Research Institute

Hong-Wei Huang

Ke-Horng Chen

Sy-Yen Kuo

Li-Ren Huang

Ruei-Ming Gan

The invention provides DC-DC converters comprising a load sensor, a variable Power MOS, and a Power MOS width controlling and driving device. The Power MOS width controlling and driving device is coupled between the load sensor and the variable Power MOS. The variable Power MOS comprises a plurality of PMOS transistors coupled in parallel and a plurality of NMOS transistors coupled in parallel. After the load sensor detects the load current of the DC-DC converter, the Power MOS width controlling and driving device conducts the PMOS and NMOS transistors according to the sensed load current to control the total size of the conduction paths that couple a transformed DC voltage output terminal to a source of an original DC voltage or ground.

DC-DC converter

A power supply apparatus for supplying an output voltage to a load is provided, which comprises a power output unit, a feedback unit and a control unit. The power output unit adjusts and supplies the output voltage to the load in accordance with at least one driving signal. The feedback unit dynamically detects output condition of the power output unit and outputs the corresponding detection result. The control unit determines a skipping ratio for an internal clock in accordance with the detection result output from the feedback unit, and outputs the internal clock with a part of the pulses being skipped to act as the driving signal.

Power supply apparatus

A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELL(0&#x3c;x&#x2266;n). The delay cells DCELL&#x2dc;DCELLare connected in series to each other. Each of the delay cells DCELLis coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal t(0&#x3c;y&#x2266;n) of a delay cell DCELLamong the delay cells DCELL&#x2dc;DCELLused as output terminal of the delay line.

Delay line, analog-to-digital converting device and load-sensing circuit using the same

A DC-DC converter includes an error amplifier that includes an operational transconductance amplifier (OTA), a compensation circuit, and a fast transient controller. The OTA includes a compensation resistor, a compensation capacitor of C, and a Miller circuit. The equalization capacitance generated by the compensation capacitor and the Miller circuit is (1+k) C. The Miller circuit includes three transistors operated in the triode region. The ratio of the current through the transistors is 1:mk:(1&#x2212;m)k. The current through the compensation capacitor in a second mode is (1+mk) times that in a first mode. The fast transient controller switches the Miller circuit between the first and second modes according to a feedback voltage dependent on the output voltage of the DC-DC converter.

Growing community of inventors

Taichung County, Taiwan

Hong-Wei Huang