Intel Corporation

Intuit, Inc.

Sipix Imaging, Inc.

Other

Hong Wang

Gautham N Chinya

Perry H Wang

John Thomas Shen

Per H Hammarlund

John P Shen

Xiang Chris Zou

Bryant E Bigbee

Richard A Hankins

Baiju V Patel

Xinmin Tian

James Paul Held

Prashant Sethi

Shivnandan D Kaushik

Jamison D Collins

Edward Thomas Grochowski

Milind Baburao Girkar

Gad Shlomo Sheaffer

Anil Aggarwal

Sanjiv M Shah

Gerolf F Hoflehner

Scott Dion Rodgers

Sreenivas Subramoney

Quinn Able Jacobson

Ralph Michael Kling

Chris J Newburn

John L Reid

Jason W Brandt

Wei Ey Li

Dion Rodgers

Partha Kundu

Tin-Fook Ngai

Robert Geva

Daniel M Lavery

Ryan N Rakvic

Robert P Knight

Trung Am Diep

Hong Jiang

Ittai Anati

Asit K Mallick

Jayesh Gaur

Ethan Schuchman

Ali-Reza Adl-Tabatabai

Doron Orenstein

Vivek K De

Kshitij Arun Doshi

Konrad K Lai

Matthew C Merten

Ronak Singhal

Belliappa Manavattira Kuttanna

Jared Warner Stark, Iv

Paul M Petersen

Yuval Yosef

Suresh Srinivas

Deepak A Mathaikutty

Zeev Sperber

Rong-Chang Liang

Guei-Yuan Lueh

Arifur Rahman

Bratin Saha

Ernie F Brickell

Hongmei Zang

Tsung-Han Lin

Stanislav Shwartsman

Ajay V Bhatt

Lihu Rappoport

Ying-Syi Li

George Zacharias Chrysos

Adi Yoaz

Michael A Kozuch

Ying Xie

Mark J Buxton

Anant V Nori

Pedro Marcuello

Anwar Ghuloum

Robert L Pelt

Sasikanth Manipatruni

Ian A Young

Christopher J Hughes

Tanay Karnik

Ronny Ronen

Christopher B Wilkerson

Ron Gabor

Narayan Biswal

James B Crossland

Darrell D Boggs

David Sehr

Saurabh Gupta

Robert S Chappell

Antonio Gonzalez

Douglas M Carmean

Gansha Wu

Rahul Pal

Bryan P Black

Avi Mendelson

Antonio González

Stephen J Robinson

Richard Lewis Hudson

Huichu Liu

Roni Rosner

A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.

Circuitry with adaptive memory assistance capabilities

A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Techniques for accelerating memory access operations

Certain aspects of the present disclosure provide techniques for maintaining an application through an execution platform. An example method generally includes receiving a first workflow definition of a plurality of workflow definitions associated with an application. The first workflow definition may be a workflow defining a build operation for building the application. The first workflow definition is executed to build the application by retrieving an executable binary from a binary repository, retrieving source code for the application binary from an application source code repository, building the application binary by executing the executable binary on the retrieved source code, and storing the application binary in the binary repository. A second workflow definition is received to execute the application. The second workflow is executed to execute the application by retrieving the application binary from the binary repository, and executing the retrieved application binary to run the application.

Integrated system to distribute and execute complex applications

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Programmable event driven yield mechanism which may activate other threads

Implementations of the disclosure implement timely and context triggered (TACT) prefetching that targets particular load IPs in a program contributing to a threshold amount of the long latency accesses. A processing device comprising an execution unit; and a prefetcher circuit communicably coupled to the execution unit is provided. The prefetcher circuit is to detect a memory request for a target instruction pointer (IP) in a program to be executed by the execution unit. A trigger IP is identified to initiate a prefetch operation of memory data for the target IP. Thereupon, an association is determined between memory addresses of the trigger IP and the target IP. The association comprising a series of offsets representing a path between the trigger IP and an instance of the target IP in memory. Based on the association, an offset from the memory address of the trigger IP to prefetch the memory data is produced.

Supporting timely and context triggered prefetching in microprocessors

In one embodiment, an apparatus includes: a value prediction storage including a plurality of entries each to store address information of an instruction, a value prediction for the instruction and a confidence value for the value prediction; and a control circuit coupled to the value prediction storage. In response to an instruction address of a first instruction, the control circuit is to access a first entry of the value prediction storage to obtain a first value prediction associated with the first instruction and control execution of a second instruction based at least in part on the first value prediction. Other embodiments are described and claimed.

System, apparatus and method for focused data value prediction to accelerate focused instructions

A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

Automatic predication of hard-to-predict convergent branches

A processor including an execution unit, an instruction scheduler circuit to identify a first instruction of an instruction stream, identify a second instruction on which execution of the first instruction depends, and assign a first dispatch priority value to the first instruction and the second instruction, and a dispatch circuit to dispatch, based on the first dispatch priority value, the first instruction and the second instruction to an instruction execution circuit.

Criticality based port scheduling

An apparatus and method for adaptive spatial accelerated prefetching. For example, one embodiment of an apparatus comprises: execution circuitry to execute instructions and process data; a Level 2 (L2) cache to store at least a portion of the data; and a prefetcher to prefetch data from a memory subsystem to the L2 cache in anticipation of the data being needed by the execution unit to execute one or more of the instructions, the prefetcher comprising a buffer to store one or more prefetched memory pages or portions thereof, and signature data indicating detected patterns of access to the one or more prefetched memory pages; wherein the prefetcher is to prefetch one or more cache lines based on the signature data.

Adaptive spatial access prefetcher apparatus and method

An execution platform comprising a workflow engine and an application engine is provided. A workflow definition associated with an application is received. The workflow definition is used to run an application workflow to perform an action with respect to the application, at least in part by causing an executable binary to be run by the application engine.

A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

Method and system to provide user-level multithreading

Embodiments of apparatuses, methods, and systems for misprediction-triggered local history-based branch prediction are described. In one embodiments, an apparatus includes a current pattern table and a local pattern table. The current pattern table has a plurality of entries, each entry in which to store a plurality of pattern lengths of a current pattern of one of a plurality of branch instructions. The local pattern table is to provide a first branch prediction based on the current pattern.

Misprediction-triggered local history-based branch prediction

Growing community of inventors

Fremont, CA, United States of America

Hong Wang