United Microelectronics Corp.

Hong-Tsz Pan

Ming-Tzong Yang

Tung-Po Chen

Gary Y Hong

Chung-Cheng Wu

Wen-Yi Hsieh

Cheng H Huang

Shyi-Long Shy

Water Lur

Der-Yuan Wu

Chih-hsun Chu

Bing-Chang Wu

Chun-Jen Weng

Shih-Chanh Chang

Ming-Tzung Yang

Yueh-Lin Chou

Cedric Lee

Lawrence Y Lin

Yeong-Song Yen

Juan-Yi Chen

Wen-An Loong

Guey-Chi Guo

Shin-Wei Sun

Jackson Lin

Ying-Chung Tseng

A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

Gap-filling process

A process for forming high temperature stable self-aligned suicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal suicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal suicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Process for forming high temperature stable self-aligned metal silicide layer

A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Salicide formation process

The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first mask layer is oxidized into a protective oxide layer during thermal oxidation for forming a liner oxide layer. The protective oxide layer can protect the top corner of a trench from he formation of pits during subsequent etching for removing a pad oxide layer, thereby preventing a kink effect. Furthermore, after forming the liner oxide layer and before filling the trench with an insulting layer, a buffer layer formed over a substrate not only prevents the sidewalls of the trench from oxidizing, but also prevents a lateral etching damage during subsequent etching for removing the pad oxide layer.

Method forming shallow trench isolation

A process for forming high temperature stable self-aligned silicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal silicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal silicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Process for forming high temperature stable self-aligned metal silicide

A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

A method for improving the planarization of a dielectric layer in the fabrication of metallic interconnects wherein a rapid thermal processing operation is used in order to consolidate exposed surfaces of a dielectric layer after local planarization of the dielectric layer. This method avoids damage to the dielectric layer caused during a pre-metal etching operation, and consequently, prevents residual tungsten from becoming lodged in fissures during subsequent tungsten deposition to produce stringers which may cause short circuiting on coming in contact with metal wiring.

Method for improving the planarization of dielectric layer in the

A method of reducing the loss of metal silicide in pre-metal etching which includes the following steps. A polysilicon gate electrode and implanted source/drain electrodes are formed on a silicon substrate. A metal silicide layer is formed on the polysilicon gate electrode and the source/drain electrodes. On the surface of the substrate, the polysilicon gate electrode, the source-drain electrodes region and the metal silicide layer, a protecting glass for insulation is formed and then dry etched to form a contact window. The metal silicide layer will form a damaged metal silicide layer in the contact window. Thereafter, a thermal process is conducted to repair the damaged metal silicide layer and finally, pre-metal etching is conducted completing the process. Pursuant to this method, the extremely low resistance of the metal silicide remains.

Method of reducing loss of metal silicide in pre-metal etching

A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained. Finally an active layer mask with a dummy pattern is obtained by performing an OR operation on the fourth pattern area and the diffusion area pattern.

Active layer mask with dummy pattern

A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprising

Single polysilicon neuron MOSFET

A method of automatically generating dummy metals for multilevel interconnection makes use of a quantum array pattern accompanying an operating pattern to from a metal pattern. The method comprises the combination selected from intersection (AND), union (OR), oversizing, downsizing, or incorporation operation through computer-aided design (CAD). Therefore, the application of the metal pattern to a process for fabricating a multimetal structure can acquire full planarization between two metal layers because of the arrangement that several dummy metals are positioned among the metal lines to diminish the spacing which exceeds the planarization limit. Also, the dummy metals are shaped in blocks thereby preventing the loading effect during etching and decreasing the parasitic capacitance therebetween.

Method of automatically generating dummy metals for multilevel

A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by:

Method of forming MOSFET devices with buried bitline capacitors

This invention describes the use and method of fabrication of a chromeless quantum phase shift mask and of a chromeless quantum phase shift build-on blank. The build-on blank can be readily inspected, stored for future use, and completed with a feature pattern when needed. The quantum phase shift mask provides improved image resolution and depth of focus tolerance. The quantum phase shift mask requires little or no CAD, or computer aided design, modification over that used for conventional masks.

Quantum chromeless lithography

This invention describes the use and methods of fabrication of a double destruction phase shift mask. The double destruction phase shift mask combines transparent phase shifting regions and attenuating phase shifting regions to form interference patterns in light projected through the mask which reduce the light intensity to nearly zero in the regions of the projected light corresponding to pattern elements. This eliminates the ghost line which can occur with conventional phase shifting masks. The double destruction phase shift mask provides improved depth of focus and edge definition.

Double destruction phase shift mask

The method is for manufacturing sealed vacuum field emission devices. A field EMITTER TIP is formed on a silicon substrate. A first dielectric layer is formed over the field EMITTER TIP and over the silicon substrate. The first dielectric layer is planarized to provide a smooth top surface co-planar with the top of the field EMITTER TIP. A grid metal layer is formed over the first dielectric layer. A second dielectric layer is formed over the grid metal layer. The second dielectric layer is patterned to provide an opening, vertically located over the field emission device, to the grid metal layer. The grid metal layer is patterned in the area defined by the opening. The first dielectric layer is removed in the region defined by the opening, and also a portion of the first dielectric layer under the grid metal layer. The upper portion of the opening is narrowed. A second metal layer is formed over the second dielectric layer and over the opening, in a vacuum environment, such that the field EMITTER TIP is in a sealed vacuum.

Growing community of inventors

Hsinchu Hsien, Taiwan

Hong-Tsz Pan