Lsi Logic Corporation

Lsi Corporation

Hong Tee Lim

Qwai Hoong Low

Maurice O Othieno

Wee Keong Liew

Chengyu Guo

Aritharan Thurairajaratnam

Manickam Thavarajah

Pradip Dhirajlal Patel

An integrated circuit (IC) package comprises a package substrate, an IC die mounted on the package substrate, a wire bond electrically connecting the IC die and the package substrate, and a heat spreader mounted on the package substrate. The heat spreader comprises a hole through a portion thereof. The IC die and the wire bond are disposed substantially between the heat spreader and the package substrate.

Heat spreader in integrated circuit package

The present invention is directed toward systems, packages, and methods for providing improved thermal performance in such packages and systems. Embodiments of the invention include a semiconductor integrated circuit (IC) package having a substrate with a heat spreader mounted on the substrate. An IC die is mounted to the heat spreader such that the heat spreader lies in between the die and the substrate. The invention is also directed to a heat spreader plate useable in a semiconductor package. The heat spreader plate comprises a plate comprised of thermally conductive material suitable for attachment to a packaging substrate wherein the plate includes openings for exposing electrical bonding surfaces of a packaging substrate when the heater spreader plate is mounted on the packaging substrate. Such openings enable wirebonding between the exposed electrical bonding surfaces of the substrate and an integrated circuit die to complete construction of a package including the heatspreader.

Integrated heatspreader for use in wire bonded ball grid array semiconductor packages

A BGA package having a multiplicity of power segments configured for power connection to integrated circuit die is disclosed. The BGA package substrate includes an integrated circuit die and a ground ring. The substrate also includes a first power ring with a plurality of spaced apart first power ring segments arranged around the die. A second power ring having a plurality of spaced apart conductive second ring segments is also formed around the die. A plurality of vias that penetrate through the substrate are provided to accommodate electrical connections to the segments of the first and second power rings and to the ground ring. The package includes bonding wires for connecting the die to the first and second ring segments and ground ring. Additionally, the package is commonly encapsulated to protect the die and wires. In some implementations, the conductive first ring segments are arranged in staggered configuration relative to the conductive second ring segments with each of the first ring segments having a conductive tab configured so that it passes through spaces between the conductive second ring segments. The tabs electrically connecting the first ring segments to vias.

Integrated circuit package and method for a PBGA package having a multiplicity of staggered power ring segments for power connection to integrated circuit die

A two layer PBGA which includes a metal ground plane at its bottom layer. The ground plane is preferably a metal plane which is connected to ground through a metal connection to a ball pad at the center of the package and a ball pad proximate the edge of the package. The ground plane is voided around the signal and power balls, via and &ldquo;dog bones&rdquo;. The PBGA is configured such that the ground plane serves effectively the same function as the second layer ground plane in a conventional four layer PBGA. The PBGA provides a cheaper alternative to the generally more expensive four layer PBGA, and provides better cross talk performance (especially for high frequency signaling) as well as better thermal performance as a result of having more metal at the bottom layer of the package.

Ground plane on 2 layer PBGA

A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole. The parasitic capacitance of the via is reduced by not having via lands on the secondary layers.

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San Jose, CA, United States of America

Hong Tee Lim