Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Hong-suk Kim

Jae-young Ahn

Ki-Hyun Hwang

Si-Young Choi

Ji-Hoon Choi

Seung-Jae Baik

Sung-Gil Kim

Seul-ye Kim

Jong-hyun Ryu

Sang-Jin Hyun

Han-jin Lim

Yong-ho Kim

Dong-hyun Sohn

Jin Ra

Hun-hyeong Lim

Moon-il Jung

Joo-ho Kim

Phil-ouk Nam

Hyun-min Song

Sang-Hoon Lee

Jung-Hwan Kim

Yong-Seok Kim

Han-Mei Choi

Young-Seok Kim

Seung-hwan Lee

Jin-Gyun Kim

Soon-cheol Kweon

Young-Dae Kim

Joon-Suk Lee

Jun-Kyu Yang

Hyun-Jin Shin

Yong-Woo Hyung

Phil-Ouk Nam

Man-Sug Kang

Sun-jung Kim

Hee-Seok Kim

Kwang-Min Park

Sang-Ryol Yang

Ju-Wan Lim

In-Sun Yi

Sung-Hae Lee

Yong-Seok Cho

Ju-Yul Lee

Jun-Hyeok Yang

Han-Vit Yang

Joon-hyung Kwon

Myung-seob Song

Jae-Hong Park

Jin-Tae No

A cooking apparatus is disclosed. The cooking apparatus according to one exemplary embodiment of the present disclosure comprises: an inner wall for forming a cooking chamber; an outer wall for encompassing the inner wall; a microwave generating part for emitting a microwave at a passage, which is a space surrounded by the inner wall and the outer wall; and an absorbing layer absorbing the microwave to be propagated along the passage, so as to emit an infrared ray at the cooking chamber.

Cooking apparatus, control method therefor and double plate

An electronic apparatus, including an emissive display configured to provide a first image having a first image quality; a transparent display disposed on the emissive display and configured to provide a second image having a second image quality; and a controller configured to control the emissive display to provide the first image in according to first mode and control the transparent display to provide the second image according to a second mode.

Electronic apparatus including emissive display and transparent display and method of controlling same

A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.

Semiconductor device including vertical channel layer and method of manufacturing the same

A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.

Semiconductor devices

A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

Vertical memory devices and methods of manufacturing the same

A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.

Vertical-type memory device

A method of manufacturing a semiconductor device, the method including forming a structure on a substrate, the structure including a metal pattern, at least a portion of the metal pattern being exposed; forming a preliminary buffer oxide layer to cover the structure, a metal oxide layer being formed at the exposed portion of the metal pattern; and deoxidizing the metal oxide layer so that the preliminary buffer oxide layer is transformed into a buffer oxide layer.

Method of manufacturing a semiconductor device

Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

Nonvolatile memory devices and fabricating methods thereof

A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

Non-volatile memory devices with multiple layers having band gap relationships among the layers

A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

Methods of manufacturing semiconductor devices

A polarizer of a liquid crystal display device and a method for manufacturing a liquid crystal display device using the same is disclosed. The polarizer includes a main body, a protection film on the main body, and a cutting line formed on the protection film. A method for manufacturing a liquid crystal display device includes providing a liquid crystal panel and a protection film having an active region and a dummy region, the protection film including at least a cutting line in the dummy region or a boundary area between the active region and the dummy region; attaching the protection film to a polarizer; attaching the polarizer to a liquid crystal panel; and, removing the dummy region of the protection film along the cutting line from the liquid crystal panel.

Polarizer and method for manufacturing liquid crystal display device using the same

A backlight unit for a liquid crystal display device includes: at least one light source; and an inverter circuit part including a dimming test portion generating a dimming signal and turning ON/OFF the at least one light source using the dimming signal.

Backlight unit for liquid crystal display device and driving method driving the same

In a method of manufacturing a non-volatile memory device, a tunnel insulating layer may be formed on a channel region of a substrate. A charge trapping layer including silicon nitride may be formed on the tunnel insulating layer to trap electrons from the channel region. A heat treatment may be performed using a first gas including nitrogen and a second gas including oxygen to remove defect sites in the charge trapping layer and to densify the charge trapping layer. A blocking layer may be formed on the heat-treated charge trapping layer, and a conductive layer may then formed on the blocking layer. The blocking layer, the conductive layer, the heat-treated charge trapping layer and the tunnel insulating layer may be patterned to form a gate structure on the channel region. Accordingly, data retention performance and/or reliability of a non-volatile memory device including the gate structure may be improved.

Method of manufacturing a non-volatile memory device

Nonvolatile memory devices with multiple layers having band gap relationships among the layers

Growing community of inventors

Yongin-si, South Korea

Hong-suk Kim