Samsung Electronics Co., Ltd.

Hong-soo Kim

Jung-Dal Choi

Jong-Ho Lee

Kyoung-Hoon Kim

Bo-un Yoon

Chang-ki Hong

Byoung-ho Kwon

Pan-suk Kwak

Sang-youn Jo

Tae-hee Lee

Jin-sook Choi

Tae-keun Cho

Ju-Yeon Lee

Se-rah Yun

Joon-Hee Lee

Jang-Gn Yun

Sung-Hoi Hur

Jae-Duk Lee

Hoo-Sung Cho

Eun-Young Choi

Hong-uk Woo

Tae-jeoung Kim

Hwa-Kyung Shin

Seung-soo Lee

Jong-Ho Lim

Jong-kook Park

Su-in Baek

Won-chul Jang

Sei-kwon Kim

Young-suk Lee

Moo-Kyung Lee

Seung-Wook Choi

Ran-kyung Hong

So-Wi Chin

Do-jun Yang

Tae-Jeoung Kim

Min-Kyoung Kang

A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region.

Semiconductor memory device and semiconductor device

A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.

Vertical memory devices

A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

Vertical memory device and method of fabricating the same

A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.

Vertical memory devices with conductive pads supported by dummy channels with varying dimensions

A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

Semiconductor memory device

An electronic apparatus connected to a server providing real-time messaging through a messaging channel to communicate therewith is provided. The apparatus includes a client communication unit for communicating with the server and at least one external device, the electronic apparatus and the at least one external device forming a client group, and a client controller for classifying the electronic apparatus and the at least one external device in the client group into a header client connected with the messaging channel to the server and a node client, and for controlling the header client to transmit a message about the node client from the server to the node client when the message from the server is transmitted to the header client through the messaging channel.

Electronic apparatus, server, and control method of system

A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.

A server-based car security service provides for image and position information to be provided to the server. The server uses the image information to make an authorization determination with respect to the current user. When the user is determined by the server to be an unauthorized user, the server alerts the owner or primary user of the car by sending the alert to a remote user device. The user device displays the image of the current user, and the owner has the opportunity to indicate whether the user is actually an unauthorized user or whether the determination at the server was a misrecognition error. When the user is unauthorized, the owner can request real-time monitoring of the car's position, and also the image inside the car, as well as an outside-of-the-car image.

Server and method of providing server-based car security service, car device and method of using server-based car security service, user device and method of using server-based car security service

A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

Wiring structures for three-dimensional semiconductor devices

In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

Semiconductor device including dummy gate part and method of fabricating the same

A method and apparatus for receiving and providing disaster information. The method of providing the disaster information includes: classifying a disaster service district into a plurality of emergency zones according to a danger level; transmitting information regarding the plurality of emergency zones to at least one mobile terminal located within the plurality of emergency zones, and receiving a location of the at least one mobile terminal from the at least one mobile terminal; and sequentially transmitting disaster information according to the danger level, to the at least one mobile terminal in the plurality of emergency zones, based on the location of a disaster which has been received from a disaster information server, when a disaster occurs.

Method and apparatus for receiving and providing disaster information

A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure.

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Seongnam-si, South Korea

Hong-soo Kim