Hynix Semiconductor Inc.

Skhynix Inc.

Hong Sok Choi

Ki Myung Kyung

Mun Phil Park

Kyu Nam Lim

Sun Hwa Park

The semiconductor memory device includes a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to an internal node, an internal voltage generator configured to generate an internal voltage signal applied to the internal node in response to a power-up signal, and an initialization element configured to initialize the internal node in response to the power-up signal.

Semiconductor memory devices

A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.

Sense amplifier and semiconductor apparatus including the same

An input circuit is disclosed. The input circuit can include a cross voltage generating block that can be configured to perform charge-sharing on a pair of input signals whose phases are opposite to each other and generate a cross voltage, and an input buffer block that can be configured to buffer the pair of input signals at a voltage level corresponding to a voltage level of the cross voltage and generate an output signal.

Input circuit of semiconductor integrated circuit

A sense amplifier of a semiconductor device is disclosed. The sense amplifier includes first and second PMOS transistors connected to each other at sources of the first and second PMOS transistors, and first and second NMOS transistors connected to each other at sources of the first and second NMOS transistors, to detect and amplify a voltage difference between a specific bit line and a complementary bit line. The second NMOS transistor and second PMOS transistor are connected to the specific bit line via a column select switch at drains of the second NMOS transistor and second PMOS transistor. The first PMOS transistor and first NMOS transistor are connected to the specific bit line via the column select switch at gates of the first PMOS transistor and first NMOS transistor. The second NMOS transistor, the second PMOS transistor, the first PMOS transistor, and the first NMOS transistor are arranged, in this order, downstream from the column select switch.

Sense amplifier of semiconductor memory device

A word line driving circuit is described herein. The word line driving circuit comprises a pull-up transistor and pull-down transistor serially connected to each other, and a control circuit configured to turn off the pull-up transistor and to turn on the pull-down transistor in response to an active command, to enable a word line driving signal to a LOW state, to turn on the pull-up transistor and to turn on the pull-down transistor for a given period of time in response to a precharge, to precharge the word line driving signal to a HIGH state, and to turn off the pull-up transistor and pull-down transistor to float the word line driving signal after the precharge command.

Growing community of inventors

Cheongju-si, South Korea

Hong Sok Choi