Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Hong-Sing Kao

Tse-Hsiang Hsu

Meng-Ta Yang

Kuan-Hua Chao

Jun-Yan Guo

Zhichao Gong

A low dropout linear regulator, a starting method, an electronic device, and a chip are provided. Wherein the low dropout linear regulator comprises an error amplifier circuit, an over current circuit and an over-current adjustor, the starting method includes: beginning a soft-starting process of the low dropout linear regulator and turning on a first transistor and a second transistor to provide a over current to raise an output voltage of the low dropout linear regulator; maintaining the 'turn on' state of the first transistor and the second transistor and decreasing the over current according to a signal obtained from the error amplifier circuit after the output voltage of the low dropout linear regulator reaches a starting voltage of the error amplifier circuit; wherein the error amplifier circuit begins to operate when the output voltage of the low dropout linear regulator reaches the starting voltage of the error amplifier circuit.

Low dropout linear regulators and starting methods therefor

A calibration method and apparatus for current and resistance are provided, where the current calibration method includes: injecting at least one portion of a set of predetermined compensation currents into at least one of an output current of a first current source and an output current of a second current source, and dynamically adjusting a distribution of the at least one portion of the set of predetermined compensation currents until two monitored voltage drops are equal to each other, and recording a first compensation current configuration; exchanging the first and second current sources, and dynamically adjusting the distribution of the at least one portion of the set of predetermined compensation currents until the two monitored voltage drops are equal to each other, and recording a second compensation current configuration; and according to the first and second compensation current configurations, generating a resultant compensation current, for use of current compensation.

Calibration method and apparatus for current and resistance

A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.

Delay line calibration mechanism and related multi-clock signal generator

A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period according to the first delay selection signal to output a delayed pulse, and delays the calibration pulse for a calibration delay period according to the second delay selection signal to output a delayed calibration pulse. The controller is for generating the input pulse, the calibration pulse, and a reference pulse. The controller also generates the first delay selection signal, and generates the second delay selection signal according to a phase difference signal. The phase detector is for generating the phase difference signal indicating the difference between the delayed calibration pulse and the reference pulse by comparing the delayed calibration pulse and the reference pulse.

A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

Growing community of inventors

Hsinchu County, Taiwan

Hong-Sing Kao