Skhynix Inc.

Hong-Sik Kim

Young-Suk Moon

Yong-Kee Kwon

Hyung-Dong Lee

Hyung-Gyun Yang

Dong-Gun Kim

Yong-Ju Kim

Joon-Woo Kim

Young-Ook Song

Do-Sun Hong

Sang-Gu Jo

Young-Jae Jin

Jin Cheng

Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at least one channel hardware set suitable for performing a feature extraction layer operation and a classification layer operation based on input data and weight data, and a controller coupled to the channel hardware set. The controller may control the channel hardware set to perform the feature extraction layer operation and perform a classification layer operation when the feature extraction layer operation is completed.

Operation apparatus and method for convolutional neural network

A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.

Memory buffer chip, memory system and method of controlling the memory buffer chip

An integrated circuit system includes a host device; and a memory module suitable for communicating with the host device according to a first protocol, the memory module comprising: at least one memory device suitable for storing data or outputting stored data, and executing communication according to a second protocol; and a protocol converter suitable for transferring information among the host device and the at least one memory device, wherein information to be inputted to the at least one memory device is transferred by being converted according to the second protocol and information to be outputted from the at least one memory device is transferred by being converted according to the first protocol.

Integrated circuit system

A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Memory system including memories having different characteristics and operation method thereof

Memory controller, memory buffer chip and memory system

A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

System and method for operating the same

A memory controller includes a plurality of request queues for storing requests transmitted from corresponding host devices among a plurality of host devices, and a token information generation unit for generating information related to the numbers of first and second tokens corresponding to the plurality of respective host devices. The memory controller also includes a request scheduler for selecting repeatedly and sequentially the plurality of request queues, and outputting requests stored in a selected request queue, by using the first and second tokens, wherein the request scheduler outputs one request per one first token and, when first tokens are all consumed, outputs one request per one second token. The scheduler may output requests according to a first-ready first-come first-served (FR-FCFS) rule when using a first token, and output requests according to a first-ready (FR) rule when using a second token. The number of first tokens and second tokens may depend on characteristics of the host devices. A bandwidth control unit may control the number of first and second tokens based on bandwidth. The scheduler may stop outputting requests of a currently selected request queue, and output requests of a request queue corresponding to a top-priority host device.

Memory controller and request scheduling method using request queues and first and second tokens

A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache.

Semiconductor device configured to control a wear leveling operation and operating method thereof

A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

Memory system including memory controller and operation method thereof

A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Cache device and control method threreof

A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

Semiconductor device for performing test and repair operations

A data storage device may include: a data storage unit comprising a plurality of channels each having a plurality of nonvolatile memory devices; and a control unit configured to control a garbage collection operation of selecting a first block included in a first channel as a victim block and copying first data included in the first block into a second block included in a second channel that is selected.

Data storage device and operating method thereof

A semiconductor memory device may include a memory cell array, and a program and verify circuit configured to perform a write operation on the memory cell array by repeating a plurality of program and verify operations. When the write operation is stopped after a first program operation is performed according to a first program condition, the PNV circuit may perform a first verify operation corresponding to the first program operation according to a first target value, after the write operation has resumed.

Semiconductor memory device, memory system including the same, and operating method thereof

A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.

Growing community of inventors

Seongnam-si, South Korea

Hong-Sik Kim