Samsung Electronics Co., Ltd.

Korea Plant Service & Engineeering Co., Ltd

Hong Seok Cho

Seung-Pil Chung

Kyoung-Sub Shin

Jun-ho Yoon

Dong-Seok Lee

Ken Tokashiki

Dong-hyun Kim

Jeong-Dong Choe

Jeong-yun Lee

Byeong-Soo Kim

Sung-Sam Lee

Joon-Seok Moon

Hyung-yong Kim

Ki Hyun Cho

Song-yi Yang

Kung-Hyon Nam

Kyung-Rae Byun

Hong Sik Yoon

O-ik Kwon

Sang Hoon Choi

Jang Wook Lee

Min Hwan Mo

Kyong Soon Jang

The present invention relates to a machining, examination, and welding integral device for a nozzle, and more particularly, to a machining, examination, and welding integral device for a nozzle in which machining, examination, and welding can be made in the nozzle by one device. To this end, there is provided a machining, examination, and welding integral device for a nozzle including: a pair of caps provided to be separated from each other; a welding unit provided between the pair of caps to weld a junction part of the nozzle and a pipe; a examination unit coupled to one side of the welding unit to check whether the junction part is defective; and a machining unit coupled to the top of the welding unit to remove the surface of a welded portion of the junction part and/or process the welded portion of the junction part.

Machining, examination, and welding integral device for nozzle

A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

Semiconductor device and method of double photolithography process for forming patterns of the semiconductor device

Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.

Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device

Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

Method of forming recess and method of manufacturing semiconductor device having the same

A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

Method of forming active region structure

Integrated circuit devices have a first substrate layer and a first transistor on the first substrate layer. A first interlayer insulating film covers the first transistor. A second substrate layer is on the first interlayer insulating film and a second transistor is on the second substrate layer. A second interlayer insulating film covers the second transistor. A contact extends through the second interlayer insulating film, the second substrate layer and the first interlayer insulating film. The contact includes a lower contact and an upper contact that contacts an upper surface of the lower contact to define an interface therebetween. The interface is located at a height no greater than a height of a top surface of the second substrate and greater than a height of a bottom surface of the second substrate layer.

Integrated circuit devices including a multi-layer structure with a contact extending therethrough

Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.

Method of fabricating semiconductor device and synchronous pulse plasma etching equipment for the same

Methods of forming integrated circuit devices including a multi-layer structure with a contact extending therethrough

A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.

Method of manufacturing a carbon nano-tube transistor

Growing community of inventors

Yongin-si, South Korea

Hong Seok Cho