Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Hanyang University

Soongsil University

Hong-Rak Son

Jun-Jin Kong

Pil-sang Yoon

Eun-chu Oh

Chang-Kyu Seol

Seong-Hyeog Choi

Ki-Jun Lee

Young-Geon Yoo

Hye-Jeong So

Dong-Min Shin

Dong-Hwan Lee

Jaehong Kim

Junjin Kong

Kijun Lee

Myung-Kyu Lee

Man-Keun Seo

Young-Jun Hwang

Jun Jin Kong

Jae-Hong Kim

Eun Chu Oh

Tae-Hwan Kim

Avner Dor

Moshe Twitto

Geunyeong Yu

Kyoung-Lae Cho

Bohwan Jun

Je-Hyuck Song

Yong-June Kim

Dong-Joon Shin

Yoo-cheol Shin

Sung-Rae Kim

Hyung-June Kim

Kwang-Hoon Kim

Sejin Lim

Hak-Sun Kim

Eun-cheol Kim

Dae-Wook Kim

Hee-seok Eun

Han-woong Yoo

Se-Jin Lim

Han-shin Shin

Geun-Yeong Yu

Kwang-hoon Kim

Sung-Han Jung

Dong-Whan Lee

Dong-Sup Jin

Seong-Hoon Woo

Soon-Jae Won

Jung-Soo Chung

Hyun-Seuk Yoo

Jae-Yong Son

Chang-kyu Seol

Kwang-gu Lee

A method of operating a resistive memory system including a plurality of layers may include receiving a write request and first data corresponding to a first address, converting the first address into a second address and assigning n (n is an integer equal to or larger than 2) pieces of sub-region data generated from the first data to the plurality of layers, and writing the n pieces of sub-region data to at least two layers according to the second address.

Cross-point memory device and method for converting and storing write data and associated parity to achieve uniform bit error rates

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

Memory system including field programmable gate array (FPGA) and method of operating same

An error correcting circuit receives a codeword including user data and a parity code, and performs an error correction operation on the user data. The circuit includes a first buffer, a decoder, a second buffer and a processor. The first buffer stores the codeword and sequentially outputs pieces of subgroup data obtained by dividing the codeword. The decoder generates pieces of integrity data for each of the pieces of subgroup data received from the first buffer, and performs the error correction operation on the user data using the parity code. The second buffer sequentially stores the pieces of integrity data for each of the pieces of subgroup data. The processor determines whether an error is present in the codeword based on the pieces of integrity data stored in the second buffer when at least one of the pieces of integrity data is updated in the second buffer.

Error correcting circuit performing error correction on user data and error correcting method using the error correcting circuit

A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.

Method of operating memory controller for performing encoding and decoding by using a convolution-type low density parity check code

A method of setting a read voltage by a memory controller and a storage device are provided. The method includes controlling a memory device to read data from memory cells by applying a test read voltage to a selected word line; receiving, from the memory device, cell count information corresponding to a read operation of the memory device, and renewing the test read voltage by using the cell count information and a cost function to find an optimum read voltage, the cost function being determined for each read voltage level; and determining a read voltage by performing the controlling of the memory device and the renewing of the test read voltage at least once.

Memory controller, method of operating the same and storage device including the memory controller

An apparatus that receives a non-binary polar code through a channel includes a low-complexity decoder and a memory. The low-complexity decoder is configured to selectively calculate first common terms for input symbols in the non-binary polar code other than a first input symbol corresponding to a first target output symbol. The selective calculation uses a lower triangular kernel and log likelihood ratios of the input symbols generated based on a channel characteristic of the channel. The low-complexity decoder is also configured to calculate log likelihood ratios of the first target output symbol using the first common terms and to determine a value of the first target output symbol based on the log likelihood ratios of the first target output symbol. The memory is accessible by the low-complexity decoder and is configured to store the first common terms.

Apparatus that receives non-binary polar code and decoding method thereof

Resistive memory device and resistive memory system including a plurality of layers, and method of operating the system

A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Memory controller for controlling memory device based on erase state information and method of operating the memory controller

A method of decoding a low density parity check (LDPC) code, includes dividing a parity check matrix of the LDPC code, into a plurality of sub blocks. The method further includes, for each of a plurality of decoding iterations, performing a node operation of each of target sub blocks among the plurality of sub blocks, the target sub blocks corresponding to a present decoding iteration among the plurality of decoding iterations, in a decoding schedule, estimating a reliability of each of the target sub blocks, based on a result of the node operation of each of the target sub blocks, and adjusting the decoding schedule, based on the reliability of each of the target sub blocks.

Method of decoding low density parity check (LDPC) code, decoder and system performing the same

A method of operating a memory system, having a non-volatile memory device, includes processing a response to a first request toward the memory device by using an original key, in response to the first request, generating and storing first parity data corresponding to the original key, and deleting the original key.

Memory device, memory system, and method of operating the memory system

Memory Controller for controlling memory device based on erase state information and method of operating the memory controller

Provided are methods for operating a non-volatile memory controller. A method for operating a non-volatile memory controller includes dividing data provided from a host into first unit data and second unit data, encoding the first unit data into first codewords including n number of bits (n is an integer equal to or more than 1), encoding the second unit data into second codewords including n-w number of bits (w is an integer less than n and equal to or more than 1) corresponding to a bit having a value of 0 among the n number of bits of the first codewords, performing bit-to-state mapping on the first codewords and the second codewords using a predetermined bitmap, and programming the first codewords and the second codewords to a first page and a second page of a non-volatile memory, respectively.

Method for operating non-volatile memory controller

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Anyang-si, South Korea

Hong-Rak Son