Samsung Electronics Co., Ltd.

Other

Samsung Display Co., Ltd.

Hong Rak Son

Junjin Kong

Jun Jin Kong

Changkyu Seol

Dong-Min Shin

Eun Chu Oh

Yong June Kim

Pilsang Yoon

Seonghyeog Choi

Jaehong Kim

Jae Hun Jang

Seong Hyeog Choi

Ki Jun Lee

Bohwan Jun

Hyejeong So

Heon Hwa Cheong

Se Jin Lim

Jae Hong Kim

Kyoung Lae Cho

Younggeon Yoo

Geunyeong Yu

Beom Kyu Shin

Chang Kyu Seol

Dongsup Jin

Kijun Lee

Youngjun Hwang

Kangseok Lee

Jung Soo Chung

KyoungLae Cho

Man Keun Seo

Youngsuk Ra

Dong Min Shin

Han Woong Yoo

Kwanghoon Kim

Taehyun Song

Mankeun Seo

Yeong Geol Song

Donghwan Lee

Daeseok Byeon

Seung-Hwan Song

Jisu Kim

Jinman Han

Heeseok Eun

Young-Seop Shim

Pil Sang Yoon

Min Uk Kim

Hyunseung Han

JongHa Kim

Jungsoo Chung

Dongjin Shin

Jinbae Bang

Wi Jik Lee

Yongjune Kim

Hee Youl Kwak

Euncheol Kim

Young Jun Hwang

Dong Hwan Lee

Sunghye Cho

Sang Hoon Lee

Heewon Lee

Avner Dor

Kwang Ho Kim

Minuk Kim

Moshe Twitto

Sae-Young Chung

Jinsoo Lim

Kwanwoo Noh

Dohyeon Kim

Sang Myeon Han

Chanho Yoon

Seonghoon Woo

Beomkyu Shin

Seungkyung Ro

Kyeongcheol Yang

Donggi Lee

Jiyoup Kim

Chan Ik Park

Seongnam Kwon

Sang Yong Yoon

Daewook Kim

Hee Seok Eun

Hanbyeul Na

Young Bae Kim

Kwang Hoon Kim

Sang Kyoo Jeong

Sung-Rae Kim

Myung Kyu Lee

Young Su Park

Sejin Lim

Moshe Schwartz

Hyeonjong Song

Hee Chang Cho

Tae Hyun Song

Bumseok Yu

Amir Bennatan

Heeyoul Kwak

Jin Soo Lim

Soonyoung Kang

Yongsung Kil

Han Shin Shin

A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

Error correcting code encoding circuit and semiconductor device including the same

Provided is an operating method of a memory controller which comprises receiving first decision data of M bits from a memory device, where M is a natural number; converting the M-bit first decision data into second decision data of N bits, where N is a natural number less than M; and attempting a first decoding using the second decision data.

Memory controller, storage device and operating method of memory controller

The present disclosure provides method and apparatuses for managing memory of storage system. In some embodiments, a controller of a storage system includes a memory storing a program, and a processor configured to execute the program to determine whether a type of data stored in the memory is at least one of a first data type and a second data type, store, in the memory, a header of the data stored in the memory, based on a first determination that the data stored in the memory is of the first data type, compress the data stored in the memory, based on a second determination that data stored in the memory is of the second data type, and power off the memory based on at least one of the header of the data and the compressed data having been stored in the memory.

Method and apparatus for managing memory of storage system

Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.

Storage device performing error correction and operating method of storage device

Disclosed herein are operation methods of a memory controller which controls a memory device. The method includes storing write data in a first area of the memory device, extracting first error position information indicating a position of at least one error included in data stored in the first area, storing the first error position information in a second area of the memory device, reading read data from the first area of the memory device, reading the first error position information from the second area of the memory device, refining the read data based on the first error position information to generate refined data, performing soft decision decoding based on the refined data to generate corrected data, and outputting the corrected data.

Operation method of memory controller configured to control memory device

A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.

Memory device and method for data encryption/decryption of memory device

a G-LDPC decoder is provided. The G-LDPC decoder includes: a generalized check node decoder configured to, in each of a plurality of iterations: group connected variable nodes into groups, the connected variable nodes being connected to an mgeneralized check node among generalized check nodes; generate test patterns in each of one or more of the groups based on a first message received by the mgeneralized check node from the connected variable nodes; and identify a value of a second message to be provided from the mgeneralized check node to the connected variable nodes based on the test patterns; and a LDPC decoder circuitry configured to, in each of the iterations, update a value of an nvariable node, among the variable nodes, based on the second message received by the nth variable node from a generalized check node that is connected to the nth variable node.

G-LDPC decoder and G-LDPC decoding method

A method of operating a storage controller includes receiving raw data indicating a series of bits each corresponding to one of threshold voltage states, performing a first state shaping for reducing a number of first target bits of the series of bits, logical values of the first target bits being equal to a logical value of a target threshold voltage state of the threshold voltage states in a first page of plural pages, generating first indicator data that indicates the first target bits based on the first state shaping, compressing the first indicator data, and storing the compressed first indicator data.

Storage controller compressing indicator data, storage device including the same, and method of operating the same

A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

Neural processing unit and electronic apparatus including the same

A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ioperation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ioperation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Decoder performing iterative decoding, and storage device using the same

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Error correction circuit and method for operating the same

A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.

Storage device and operating method of storage device

A storage device includes a nonvolatile memory device and a memory controller. The memory controller receives first data from the nonvolatile memory device based on a first read command, and performs error correction on the first data. When the error correction fails, the memory controller transmits a second read command and second read voltage information to the nonvolatile memory device, receives second data from the nonvolatile memory device, transmits a third read command and third read voltage information to the nonvolatile memory device, and receives third data from the nonvolatile memory device. The memory controller adjusts an offset based on the second data and the third data, transmits a fourth read command, fourth read voltage information, and the offset to the nonvolatile memory device, receives fourth data from the nonvolatile memory device, and performs a soft decision process based on the fourth data.

A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by 'k' states (k being an integer greater than 2) smaller in number than the 2states, performs first error correction encoding on the second write data to generate third write data expressed by the 'k' states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.

Storage device that performs state shaping of data

Growing community of inventors

Anyang-si, South Korea

Hong Rak Son