Intel Corporation

Hong-Piao Ma

Keng L Wong

Greg F Taylor

Edward Allyn Burton

Chee How Lim

Robert J Greiner

Douglas Robert Huard

George L Geannopoulos

Niraj Bindal

An apparatus is provided that includes a clock distribution network, a plurality of distributed oscillators provided about the clock distribution network so as to provide clock signals on the clock distribution network and a power control circuit to control power applied to the plurality of distributed oscillators. The power control circuit includes a bandgap device to produce a reference voltage based on a desired power level and a comparing/decision device to receive the reference voltage from the bandgap device and to receive the voltage signal from a source external to the apparatus. The comparing/decision device determines whether the signal received from the power source corresponds to the desired power level.

Voltage control for clock generating circuit

A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.

Clock generating circuit and method

An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Voltage ID based frequency control for clock generating circuit

A clock generating circuit is provided that includes a plurality of distributed ring oscillators to drive a clock distribution network. Multiplexing devices may select a length or delay of each of the ring oscillators. The variable length or delay may thereby adjust the frequency of the clock generating circuit.

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Portland, OR, United States of America

Hong-Piao Ma