Samsung Electronics Co., Ltd.

Hong-mook Choi

Jong-hoon Shin

Sang-Hyun Park

Ji-su Kang

Hye-soo Lee

Xingguang Feng

Yun-Ho Youm

Jae-hyeok Kim

Hyun-il Kim

Jaechul Park

Mi-jung Noh

Heonsoo Lee

Jin-su Hyun

Heon-Soo Lee

Youngjin Chung

Jisoo Kim

Dong-jin Park

Jae-Chul Park

Jonghoon Shin

Hyo-sun Hwang

Yong-ki Lee

Young-jin Chung

Heon Soo Lee

Woo-Hyun Lee

Ki-Seok Bae

Hyesoo Lee

Ingoo Heo

Ki-seok Bae

Hyun Il Kim

Jaejoon Choi

JuHyung Hong

Ju-Hee Park

Hye Soo Lee

Hyun-woong Lee

Kwangho Yoo

Hoyou Jun

Seok-Min Park

Yong-Ki Lee

Storage devices are provided which include a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory controller includes a plurality of encryption and decryption cores, the plurality of encryption and decryption cores perform initialization at the same time and generate a plurality of initial tweak values, sequentially select the plurality of initial tweak values to perform encryption or decryption, and perform the encryption or the decryption in parallel by using one or more initial tweak values selected from the plurality of initial tweak values.

Storage device and operating method of storage device

An encryption device for performing virtual and real operations and a method of operating the encryption device. The method includes performing a virtual operation; when a real operation request signal is received, determining whether the virtual operation being performed is completed; and in response to the virtual operation being completed, performing a real operation in response to the real operation request signal.

Encryption device and operation method thereof

Provided are a security processor for performing a remainder operation by using a random number and an operating method of the security processor. The security processor includes a random number generator configured to generate a first random number; a modular calculator configured to generate a first random operand based on first data and the first random number and generate output data through a remainder operation on the first random operand, wherein a result value of the remainder operation on the first input data is identical to a result value of the remainder operation on the first random operand.

Security processor performing remainder calculation by using random number and operating method of the security processor

An encryption device includes a counter, an encryption/decryption unit, and a timer. The counter is configured to generate a first timestamp for a first time. The encryption/decryption unit is configured to concatenate security data and the first timestamp, encrypt the concatenated data into encryption data, transmit the encryption data to a memory device, and decrypt read data transmitted from the memory device into decryption data. The timer is configured to inform the counter and the encryption/decryption unit that a time elapses from the first time to a second time such that the counter generates a second timestamp for the second time and the encryption/decryption unit decrypts the read data into the decryption data. Checking logic implemented by the encryption device is configured to check whether a decryption timestamp of the decryption data is identical to the first timestamp.

Encryption device for encrypting data and timestamp, system on chip including the same, and electronic device

An encryption circuit includes a pipelined encryption core having a plurality of round cores therein. The pipelined encryption core is configured to perform a real round operation on each of a plurality of pieces of input data received therein and generate encryption data from the input data using an encryption operation comprising the real round operation. An encryption controller is provided, which is coupled to the pipelined encryption core. The encryption controller is configured to control the pipelined encryption core so that at least one of the plurality of round cores performs a virtual round operation as part of the encryption operation. The pipelined encryption core is configured to perform a virtual encryption operation using at least one of: (i) dummy data, and (ii) a dummy encryption key.

Encryption circuit for performing virtual encryption operations

A method of testing using a memory test apparatus connected to a memory device includes receiving a test command. When the test command is a finite state machine (FSM) operation command, the memory device is tested in accordance with the FSM operation command, and an operation is performed to output a result depending on a pass/fail result. But, when the test command is a direct access command, an auto-operation test of input data is performed in a test region according to received address information, and a test result is output, which may include output data with fail information or the auto-operation.

Memory test apparatus and testing method thereof including built-in self test (BIST)

A security device providing a security function for an image, a camera device including the same, and a system on chip (SOC) for controlling the camera device are provided. An image transmitting device may include an image processor configured to process an image to be transmitted to an external device, and a security circuit including a key shared with the external device. The security circuit may be configured to generate a tag used for image authentication by using data of a partial region of the image and the key based on region information for selecting the partial region of the image. The image transmitting device may be configured to transmit the tag, generated to correspond to the image, to the external device with data of the image.

Security device for providing security function for image, camera device including the same, and system on chip for controlling the camera device

A security device includes a secure processor, a mail box, a cryptographic intellectual property (IP), a secure direct memory access (DMA) circuit, and an internal memory. The secure processor provides an isolated execution environment. The mail box transfers a request from a CPU to the secure processor. The cryptographic IP performs one or more secure operations, including a signature certification operation, an encryption/decryption operation, and an integrity verification operation, on secure data within the isolated execution environment and without intervention of the CPU. The secure DMA circuit controls the one or more secure operations within the isolated execution environment, wherein only the secure processor is configured to control the secure DMA circuit. The internal memory stores the secure data on which the one or more secure operations are performed. The cryptographic IP includes a DMA circuit configured to control data access to an external storage.

Security devices, electronic devices and methods of operating electronic devices

An electronic circuit includes an operator including logic gates configured to perform either one or both of encryption and decryption operations. The electronic circuit further includes a controller configured to control the operator to operate in a first mode in which each of the logic gates outputs a first logic value during a first time period of a clock signal, and operate in a second mode in which a number of first logic gates, each of which outputs the first logic value, among the logic gates, and a number of second logic gates, each of which outputs a second logic value, among the logic gates, are maintained constant during a second time period of the clock signal, in response to a control value indicating that either one or both of the encryption and decryption operations are performed.

Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same

A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.

Computing system having an on-the-fly encryptor and an operating method thereof

A method for encryption, decryption, or encryption and decryption of data in a crypto device having at least one crypto core may include: generating a tweak value corresponding to block data, which is placed at a random position from which the encryption, decryption, or encryption and decryption starts, from among sequential block data; and/or performing the encryption, decryption, or encryption and decryption from the block data using the tweak value. A method for encryption, decryption, or encryption and decryption of block data may include: generating a tweak value corresponding to the block data at a random position; and/or performing the encryption, decryption, or encryption and decryption of the block data using the tweak value.

Crypto devices, storage devices having the same, and encryption and decryption methods thereof

An endecryptor and a control device are provided. The endecryptor includes a first SBOX configured to replace first input data with first substitution data, a transformation unit configured to replace the first input data with second substitution data and an output terminal configured to output encrypted or decrypted output data based on the first and second substitution data.

Endecryptor preventing side channel attack, driving method thereof and control device having the same

An encryptor/decryptor, an electronic device including the encryptor/decryptor, and a method of operating the encryptor/decryptor are provided. The method of operating the encryptor/decryptor includes distributing an input plaintext stream to a plurality of encryption/decryption cores by pieces of plaintext data; performing a first operation by a first encryption/decryption core from among the plurality of encryption/decryption cores; and encrypting the plaintext data to ciphertext data or decrypting the ciphertext data to the plaintext data by each of the plurality of encryption/decryption cores by using a result of performing the first operation in the first encryption/decryption core.

Encryptor/decryptor, electronic device including encryptor/decryptor, and method of operating encryptor/decryptor

A host controller that controls a storage device includes an encryption unit that is selectively configured in response to file encryption information and disk encryption information to encrypt data. The encryption unit encrypts the data using a file encryption operation based on the file encryption information and/or a disk encryption operation based on the disk encryption information.

Host controller and system-on-chip

A method of operating a system on chip (SoC) includes converting plain data into cipher data by using an encryption key and transmitting the cipher data directly to a memory controller which controls an operation of a non-volatile memory. The encryption key may be output by a one-time programmable (OTP) memory.

Growing community of inventors

Bucheon-si, South Korea

Hong-mook Choi