Samsung Electronics Co., Ltd.

Hong-Mi Park

In-Sun Park

Hyeon-Deok Lee

Ju-Cheol Shin

Ji-hong Kim

Tae-hyuk Ahn

Jong-Myeong Lee

Jeong-Sic Jeon

Jong-Sik Chun

Jun-Sik Hong

Young-sun Cho

A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate

In a method of manufacturing a semiconductor device, a tungsten layer pattern having an oxidized surface is formed on a substrate. A source gas including silicon is provided to the oxidized surface of the tungsten layer pattern to form a protecting layer on the oxidized surface of the tungsten layer pattern. The protecting layer prevents an abnormal growth of oxide contained in the oxidized surface. The protecting layer prevents a whisker from growing from the oxidized surface of the tungsten layer pattern.

Method of manufacturing a semiconductor device

An integrated circuit includes a substrate and a first insulating layer on the substrate that includes a first hole including a floor and a sidewall. A first conductive contact extends conformally on the sidewall and floor to define a groove in the first hole. A second insulating layer is provided on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is provided in the second hole and in the groove. These integrated circuits are fabricated by forming a first insulating layer on a substrate that includes a first hole including a floor and a sidewall. A first conductive contact is conformally formed on the sidewall and floor to define a groove in the first hole. A second insulating layer is formed on the first insulating layer and includes a second hole that exposes the groove. A second conductive contact is formed in the second hole and in the groove.

Methods of fabricating integrated circuit conductive contact structures including grooves

In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

Method of forming a contact in a semiconductor device

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Seoul, South Korea

Hong-Mi Park