Promos Technologies, Inc

Mosel Vitelic Corporation

Seimens Aktiengesellschaft

Hong-Long Chang

Ming-Li Kung

Chun-Wei Chen

Hungyueh Lu

Fang-Fei Liu

Yueh-Chuan Lee

Ray C Lee

Nien-Yu Tsai

Nien-yu Tsai

Chin-Long Hung

Hung-Yueh Lu

A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.

Volatile memory devices and methods for forming same

A dry cleaning method for use in semiconductor fabrication, including the following steps. An etched metallization structure is provided and placed in a processing chamber. The etched metallization structure is cleaned by introducing a fluorine containing gas/oxygen containing gas mixture into the processing chamber proximate the etched metallization structure without the use of a downstream microwave while applying a magnetic field proximate the etched metallization structure and maintaining a pressure of less than about 50 millitorr within the processing chamber for a predetermined time.

Dry clean method instead of traditional wet clean after metal etch

A post-cleaning method of a via etching process for cleaning a wafer, the wafer having a tungsten (W) layer, an oxide layer covered on the tungsten layer, a photoresist layer patterned on the oxide layer, and a via passing through the photoresist layer and the oxide layer until a predetermined area of the tungsten layer is exposed, the cleaning method has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; (b) performing a dry cleaning process which uses CF and N H as the main reactive gas; and (c) performing a water-rinsing process.

Post-cleaning method of a via etching process

A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; removing the photoresist layer in an asher using a combination of oxygen plasma and water vapor, the ratio of oxygen plasma and water vapor being less than one; and performing a wet strip on the metal interconnect structure.

Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer

A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer layers. The third etch step is performed using a B and Cl containing gas and a Cl containing gas. In an important fourth etch step (D), we remove the first, second and third polymers; the fourth etch step performed using only chlorine containing gas (Cl ) gas and a fluorocarbon containing gas.

Defects reduction for a metal etcher

A method of forming a metal interconnect structure and via plugs over a dielectric layer having a plurality of vias formed therein is disclosed. The method comprises the steps of: forming tungsten via plugs in the plurality of vias; depositing a metal layer over the dielectric layer and the plurality of tungsten via plugs; patterning and etching the metal layer using a photoresist layer to form the metal interconnect structure; oxidizing the metal interconnect structure and the tungsten via plugs to form a metal oxide layer over the metal interconnect structure and tungsten via plugs; and performing a wet strip on the metal interconnect structure.

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Hsin-Chu, Taiwan

Hong-Long Chang