Lsi Logic Corporation

Lsi Corporation

Hong Lin

Shiqun Gu

Wai Lo

Verne C Hornback

Sey-Shing Sun

Richard J Carter

Wilbur G Catabay

Venkatesh P Gopinath

Zhihai Wang

Wei-Jen Hsia

Peter McGrath

Dodd Defibaugh

Ynhi Thi Le

Jim Elmer

Mohammad R Mirbedini

James R B Elmer

Masaichi Eda

Ryan Tadashi Fujimoto

A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow

Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.

Process and apparatus for simultaneous light and radical surface treatment of integrated circuit structure

A method of forming a metal gate in a wafer. PolySiGeand polysilicon are used to form a tapered groove. Gate oxide, PolySiGe, and polysilicon is deposited on a wafer. A resist pattern is formed. A portion of the polysilicon, PolySiGe, and gate oxide is removed to provide a tapered profile. The resist is removed; a dielectric liner is deposited, and then at least a portion of the dielectric liner is removed, thereby exposing the polysilicon and leaving the dielectric liner in contact with the polysilicon, PolySGe, and gate oxide. A dielectric is deposited, and a portion is removed thereby exposing the polysilicon. The polysilicon, PolySiGe, and gate oxide is removed from inside the dielectric liner, thereby leaving a tapered gate groove. Metal is then deposited in the groove.

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An improvement to an integrated circuit, of electrically conductive interconnects formed of a superconducting material. In this manner, the electrically conductive interconnects can be made very small, and yet still have adequate conductively. In various embodiments, all of the electrically conductive interconnects are formed of the superconducting material. In some embodiments, the electrically conductive interconnects are formed of a variety of different superconducting materials. In one embodiment, only the backend electrically conductive interconnects are formed of the superconducting material. In some embodiments no vias are formed of the superconducting material. The interconductor dielectric layers are preferably formed of silicon oxide, and sometimes all of the interconductor dielectric layers are formed of silicon oxide. The superconducting material is in some embodiments at least one of an organic compound such as a potassium doped buckminsterfullerene, a cesium doped buckminsterfullerene, and other carbon containing compounds, a metallic material such as an inter-metallic material like Nb&#x2014;Ti alloys and other substances formed by alloying metals, and an inorganic compound such as YBaCuO, (Pb,Bi)SrCaCuOand its derivatives, HgBaCaCuO and its derivatives, and TI&#x2014;Ba&#x2014;Ca&#x2014;Cu&#x2014;O and its derivatives.

Superconductor wires for back end interconnects

An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Interconnect dielectric tuning

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Fabrication of trenches with multiple depths on the same substrate

A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

Selective high k dielectrics removal

A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.

Plasma passivation

A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.

Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene process

In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O plasma oxidation. The presence of the sidewall oxides minimizes encroachment under the gate edge.

High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation

A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si N is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

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Vancouver, WA, United States of America

Hong Lin