Chartered Semiconductor Manufacturing Ltd (corporation)

Infineon Technologies Ag

Infineon Technologies Austria Ag

Hong Lim Lee

Sang Yee Loong

Chun Hui Low

Qiang Guo

Bei Chao Zhang

Sanjay Kumar Murugan

Jayaganasan Narayanasamy

Beichao Zhang

Jagen Krishnan

Jae Soo Park

Kok Tee Lau

Chivukula Subramanyam

Thow Phock Chua

A method for forming a matrix composite layer on a workpiece and a workpiece with a matrix composite layer are disclosed. In an embodiment the method includes forming a wall around a metallic surface such that the wall extends in a vertical direction from a plane formed by the metallic surface, and depositing a filler material in a walled area on the metallic surface. The method further includes depositing a plastic material on the filler material and performing a vacuum treatment of the filler material and the plastic material thereby forming a matrix composite layer disposed on the metallic surface.

Method for forming a matrix composite layer and workpiece with a matrix composite layer

An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Via electromigration improvement by changing the via bottom geometric profile

An integrated circuit interconnect is provided having a dielectric layer disposed between a wide top metal line and a wide bottom metal line. A via-sea in the dielectric layer connects the wide top and wide bottom metal lines by means of a first via having a width, a second via having a width and spaced more than two widths away and less than four widths away from the first via.

Via-sea layout integrated circuits

Growing community of inventors

Penang, Malaysia

Hong Lim Lee