Infineon Technologies Ag

Silicon Laboratories Inc.

Lantiq Deutschland Gmbh

Hong Lee Koo

Ingo Volkening

Jiaxiang Shi

Swee Hock Lim

Shantonu Bhadury

Bing Tao Xu

Yean Kee Yong

Jasmeet Singh Narang

Harikrishnan Prabha Valsala

A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.

System and method of masking memory read request to avoid memory read corruption

There is provided an apparatus and method for transferring data packets from a peripheral module to a memory via a memory-controller. When a given peripheral module requests that it send a data packet to the memory via the memory-controller, the memory-controller sends an acknowledgement indicating that the peripheral module can send the data packet, whether or not there is a descriptor for the data packet. If there is a descriptor, the memory-controller receives the data packet from the peripheral module and stores it in the memory. If there is not a descriptor, the memory-controller discards the data packet as it receives it. Thus, whether or not there is a descriptor available for the data packet, the peripheral module still sends the data packet to the memory-controller. The data packets may be assigned classifications and each classification may be assigned a dedicated space in the memory.

Apparatus and method for data transfer

Flow control is provided for a packet switch. An incoming packet is classified according to its priority based on predefined rules to produce a weight value based on the priority of the packet. A lifetime value associated with the packet is produced based on the weight value and the queue occupancy in a queue to which the packet is assigned. The packet is discarded if its associated lifetime value is less than or equal to a threshold value. Otherwise the packet and associated lifetime value are sent to the queue. The lifetime value is periodically changed and compared to a threshold value. The packet is removed from the queue when its lifetime value reaches the threshold value.

Random early detect and differential packet aging flow control in switch queues

A data switchincludes a switching engine, and input/output interfaceswhich each connect the switching engineto one of a number of channels. The input/output interfacesand the switching engineare each made up of a number of modules (PHY, MAC_RX, RX, MAC_TX, TX, PBM, ARL, QM). Some or all of the modules have a logic circuit for turning them on when they are required to process data packets passing through the circuit, and a logic circuit is provided for turning them off when they are no longer required. In this way the power requirements of the switchare reduced.

Reducing power consumption in data switches

There is provided a semiconductor device for multiplexing across a plurality of shared Input/Output (I/O) pins. The semiconductor device comprises a first core for operation of a first function, a second core for operation of a second function, a multiplexer and an additional hardware module. The multiplexer is arranged to set the I/O pins to the first function or to the second function at power up. The hardware module comprises an arbiter arranged to receive requests from the cores for use of the I/O pins and to grant use of the I/O pins to a selected core as required. Thus, the hardware module can switch functions dynamically and dual mode multiplexing is enabled.

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Singapore, Singapore

Hong Lee Koo