Samsung Display Co., Ltd.

Hong-kyu Kim

Seungho Park

Jung-Taek Kim

A gate driver includes M active stages configured to generate first through M-th carry signals and first through M-th gate signals based on clock signals, where M is an integer greater than or equal to 4, and K back dummy stages configured to generate (M+1)-th through (M+K)-th carry signals based on the clock signals, where K is an integer greater than or equal to 3. An N-th active stage of the M active stages discharges a control node of the N-th active stage based on an (N+3)-th carry signal, where N is an integer greater than or equal to 1, and is less than or equal to M. At least one back dummy stage of the K back dummy stages discharges a control node of the at least one back dummy stage based on a corresponding clock signal of the clock signals.

Gate driver and display device

A display device includes a data driver providing a data voltage to each of multiple pixels, a scan driver providing first and second scan signals to each of the pixels, and a controller to control the data driver and the scan driver. The scan driver performs a first active scan operation that sequentially provides the first and second scan signals to the pixels in an active period of a first frame period, and initiates a dummy scan operation that sequentially provides the second scan signal to the pixels in a blank period of the first frame period. When a second frame period starts before the dummy scan operation for the pixel in a last row, the data driver changes a level of the data voltage in an overlap period in which the dummy scan operation and a second active scan operation in the second frame period are simultaneously performed.

Growing community of inventors

Yongin-si, South Korea

Hong-kyu Kim