Samsung Electronics Co., Ltd.

Hong-kook Min

Yong-kyu Lee

Gwan-Hyeob Koh

Yong-tae Kim

Bo-young Seo

Hyok-Ki Kwon

Yong-Suk Choi

Choong-jae Lee

Aliaksei Ivaniukovich

A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

Semiconductor apparatus including magnetoresistive device

A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Semiconductor device including magneto-resistive device

A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.

Non-volatile memory device and method of manufacturing the same

A semiconductor memory device included in a system-on-chip (SOC) or a microcomputer chip. The semiconductor memory device may include a flash memory cell array unit and a mask read-only memory (ROM) cell array unit which are formed in a single memory block without an isolation layer for separating the two units. Transistors included in the flash memory unit and the mask ROM unit are the same type and may have two threshold voltages. The transistor in each memory cell unit may be a split gate transistor, a metal-oxide-nitride-oxide-silicon, or silicon-oxide-nitride-oxide-silicon transistor. Further, the transistor included in the mask ROM unit in the semiconductor memory device may include enhancement transistors or depletion transistors in which a dopant ion-implanted region is formed at channel portions.

Growing community of inventors

Yongin-si, South Korea

Hong-kook Min