Skhynix Inc.

Hong Ki Moon

Jeong Tae Hwang

Dong Hee Han

Seung Woo Lee

Seok Bo Shim

A semiconductor memory device includes a command address control circuit configured to generate an error correction command and selection address for executing an error correction operation by receiving an external control signal, an error flag generation circuit configured to correct an error of data corresponding to the selection address and configured to generate a target error flag based on a pattern of the error of the data, and an error information processing circuit configured to generate a target address that is used as the selection address based on the target error flag in a target error correction operation that is executed based on the error correction operation.

Semiconductor memory device and memory system performing error correction operation

The present technology may include a first latch circuit configured to store, as first data, data that is transmitted through a first signal line, a second latch circuit configured to store, as a plurality of second data, the data that is transmitted through the first signal line by sorting the data by a plurality of second signal lines that are connected to the first signal line in common, and a data bus inversion engine configured to selectively perform a first mode in which the data bus inversion engine generates a data bus inversion flag by comparing the first data with current input data and a second mode in which the data bus inversion engine generates the data bus inversion flag by comparing the plurality of second data with the current input data.

Data bus inversion circuit and semiconductor apparatus including the same

A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

Random pulse generator and memory

A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.

Memory device and test method thereof

A semiconductor device may be provided. The semiconductor device may include an input signal generator configured to enable an input signal although a reset signal is disabled after a clock enable signal is enabled. The semiconductor device may include a self-refresh enable signal generator configured to generate a self-refresh enable signal based on the input signal.

Semiconductor device

A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)command/address signals (wherein, 'M' denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)command/address signal and compare first to Nsensing codes (wherein, 'N' denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mcommand/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mcommand/address signals.

Semiconductor devices and semiconductor systems including the same

A fuse test mode detection device is disclosed, which relates to a technology for improving detection efficiency of a fuse test mode. The fuse test mode detection device includes: a fuse unit configured to scan a plurality of fuses in a boot-up operation, and output fuse data; a counter configured to count the fuse data in response to a clock signal; a decoding unit configured to output a decoding signal for controlling a fuse test mode in response to an output signal of the counter; an encoder configured to encode the output signal of the decoding unit, and output a code signal; and a comparator configured to compare the fuse data with the code signal, and output a comparison signal.

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Seoul, South Korea

Hong Ki Moon