Yonsei University

Qualcomm Technologies, Inc.

Hong Keun Ahn

Seung Hyuk Kang

Seong-Ook Jung

Sungryul Kim

Seong Ook Jung

Sara Choi

Ki Ryong Kim

Dong Hoon Jung

Young Kyu Lee

Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every group by applying a multi-bit weight to the stored input data; and a final summation unit which is connected to at least one multi-bit unit, adjusts a ratio for every group to receive the peer-group sum value, and outputs a final output value by summing the input per-group sum value.

In-memory device for operating multi-bit weight

An apparatus for harvesting energy includes an AC harvester having an AC harvesting capacitor and configured to extract power from an AC environment energy source, a DC harvester configured to extract power from a DC environment energy source, and a power transferrer configured to control a transfer path of power extracted from the DC harvester based on a magnitude of a voltage of the AC harvesting capacitor and a magnitude of a voltage applied from the DC harvester.

Apparatus for harvesting energy using dual environment energy source and method thereof

Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic '0' and logic '1' write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.

Offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation

Sensing voltage based on a supplied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations. Sensing voltage based on supply voltage applied to an MRAM bit cell in a write operation can be used to detect completion of magnetic tunnel junction (MTJ) switching in an MRAM bit cell to terminate the write operation to reduce power and write times. In exemplary aspects provided herein, reference and write operation voltages sensed from the MRAM bit cell in response to the write operation are compared to each other to detect completion of MTJ switching of voltage based on the supply voltage applied to the MRAM bit cell regardless of whether the write operation is logic '0' or logic '1' write operation. This provides a higher sensing margin, because the change in MTJ resistance after MTJ switching completion is larger at the supply voltage rail.

Sensing voltage based on a supply voltage applied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations to the MRAM bit cells

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Seoul, South Korea

Hong Keun Ahn