Intel Corporation

Other

Optivision, Inc.

Tahoe Research, Ltd.

Hong Jiang

Joydeep Ray

Yi-Jen Chiu

Lidong Xu

Wenhao Zhang

Yu Han

Thomas A Piazza

Ning Lu

Sang-Hee Lee

Michael K Dwyer

Zhipin Deng

Hong Wang

Guei-Yuan Lueh

Xiaoxia Cai

Val Gene Cook

Yuval Yosef

Jason Daniel Tanner

Gautham N Chinya

John Thomas Shen

James M Holland

Steven Spangler

Scott W Cheng

Prasoonkumar Surti

Baiju V Patel

Gad Shlomo Sheaffer

Per H Hammarlund

Dion Rodgers

Bryant E Bigbee

Richard A Hankins

James Paul Held

Ya-Ti Peng

Hiu-Fai R Chan

Kam Leung

Shiv Kaushik

Yoav Talgam

Benjamin Jiang Cymbala

Yan Hou

Doron Rajwan

Alon Naveh

Ron Gabor

Narayan Biswal

Atthar H Mohammed

Satya N Yedidi

Ping Liu

Niraj Gupta

Chunhui Mei

James Varga

Maxim Lukyanov

Brian D Rauchfuss

Xuefeng Zhang

Katen Shah

Yuenian Yang

Bishara Shomar

Bixia Zheng

Gady Yearim

Weiping Li

Xiaoying He

Dinakar Munagala

Sreedevi Chalasani

Altug Koker

Subramaniam M Maiyuran

David J Harriman

Varghese George

Nikos Kaburlasos

Jasmin Ajanovic

Ben J Ashbaugh

Scott R Janus

Yen-Kuang Chen

Changliang Wang

William W Macy, Jr

James A Valerio

Dipankar Das

Perry H Wang

Eric L Debes

Naveen K Mellempudi

Xinmin Tian

Igor V Kozintsev

Supratim Pal

Wishwesh Anil Gandhi

Satyaki Koneru

Jong Dae Oh

Ernest T Tsui

Fangwen Fu

Jamison D Collins

Sumit Mohan

Maximino Vasquez

Yan Li

Allen H Simon

Jian Zhou

Ramanathan Sethuraman

Dhiraj D Kalamkar

Jean-Pierre Giacalone

Changwon D Rhee

Guiren Wang

Jiasheng Chen

Chu-Cheow Lim

Vijay Sundaram

Richard W Jensen

Sabareesh Ganapathy

Matrix multiply units can take advantage of input sparsity by zero gating ALUs, which saves power consumption, but compute throughput does not increase. To improve compute throughput from sparsity, processing resources in a matrix accelerator can skip computation with zero involved in input or output. If zeros in input can be skipped, the processing units can focus calculations on generating meaningful non-zero output.

Random sparsity handling in a systolic array

Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.

Hierarchical thread scheduling based on multiple barriers

Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Methods and systems for motion vector derivation at a video decoder

An apparatus to facilitate a computer number format conversion is disclosed. The apparatus comprises a control unit to receive to receive data format information indicating a first precision data format that input data is to be received and converter hardware to receive the input data and convert the first precision data format to a second precision data format based on the data format information.

Conversion hardware mechanism

Techniques related to frame re-ordering for video coding are described herein.

Method and system of frame re-ordering for video coding

In a scalable video codec, an adaptive Wiener filter with offset aims to minimize the differences between two input pictures or picture regions, and the filter coefficients need to be transmitted to decoder site.

Adaptive filtering for scalable video coding

Methods, systems and computer program products that may improve the efficiency of the video encoding process. Mode decision processing and bit stream packing may be performed in parallel for various frames in a sequence. This reduces the amount of idle time for both the mode decision processing logic and the bit stream packing logic, improving the overall efficiency of the video encoder.

Systems, methods, and computer program products for a video encoding pipeline

Systems, apparatus and methods are described including operations for video coding including cross-layer cross-channel residual prediction.

Cross-layer cross-channel residual prediction

Methods, systems, and computer program products for the generation of multiple layers of scaled encoded video data compatible with the HEVC standard. Residue from prediction processing may be transformed into coefficients in the frequency domain. The coefficients may then be sampled to create a layer of encoded data. The coefficients may be sampled in different ways to create multiple respective layers. The layers may then be multiplexed and sent to a decoder. There, one or more of the layers may be chosen. The choice of certain layer(s) may be dependent on the desired attributes of the resulting video. A certain level of video quality, frame rate, resolution, and/or bit depth may be desired, for example. The coefficients in the chosen layers may then be assembled to create a version of the residue to be used in video decoding.

Systems, methods, and computer program products for scalable video coding based on coefficient sampling

Reconstructed picture quality for a video codec system may be improved by categorizing reconstructed pixels into different histogram bins with histogram segmentation and then applying different filters on different bins. Histogram segmentation may be performed by averagely dividing the histogram into M bins or adaptively dividing the histogram into N bins based on the histogram characteristics. Here M and N may be a predefined, fixed, non-negative integer value or an adaptively generated value at encoder side and may be sent to decoder through the coded bitstream.

Histogram segmentation based local adaptive filter for video encoding and decoding

Techniques involving inter layer prediction of scalable video coding are described. Such techniques may employ refining filters.

Refining filter for inter layer prediction of scalable video coding

A communication server and accompanying communication devices allow near instantaneous communication between users of the communication devices. A communication device may be configured with multiple channels, where each channel is assigned a corresponding communication device. As the communication devices are registered with the communication server, each communication device has knowledge of other registered communication devices. Thus, communication devices may communicate nearly instantaneously with each other. Furthermore, as the communication device is equipped with multiple channels, a single communication device may host a conference call with other communication devices. In addition, communication device may include multiple buttons to control the communication device, and indicator lights to indicate the status of calls with other communication devices.

Instant communications system having established communication channels between communication devices

Described herein are techniques related to re-use of filter parameters, and particularly Sample Adaptive Offset (SAO) parameters, of a lower-layer bitstream or a coded enhancement layer bitstream for coding enhancement layer bitstream in a scalable video encoding.

Inter-layer sample adaptive filter parameters re-use for scalable video coding

Growing community of inventors

El Dorado Hills, CA, United States of America

Hong Jiang