Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Samsung Display Co., Ltd.

Samung Electronics Co., Ltd

Hana Micron Inc.

Hong-Jae Shin

Kyoung-woo Lee

Jae-hak Kim

Nae-in Lee

Soo-geun Lee

Young-jin Wee

Seo-woo Nam

Dong-Suk Shin

Sun-Jung Lee

Byeong-jun Kim

Andrew-Tae Kim

Young-joon Moon

Jae-ouk Choo

Sung-jin Kim

Hee-Sook Park

Seung-man Choi

Kae-Dal Kwack

Woo-Jin Jang

Jin-Ho Kim

Ki-chul Kim

Tae-Whan Kim

Seung-Jin Lee

Chong-Kwang Chang

Bong-Seok Suh

Kyoung-Woo Lee

Dong-chul Kwon

Ki-Kwan Park

Hyun-dam Jeong

Seung-Il Bok

Sae-Il Son

Mi-Young Son

Jung-Hoon Lee

Sang-Wook Kwon

Hun Rae Kim

Yoon-Hae Kim

U-in Chung

Ji-hyun Choi

Jong-Sam Kim

Jeong-Hoon Ahn

Wan-jae Park

Ja-Eung Koo

Ju-seon Goo

Young-Mook Oh

Soo-Geun Lee

Byung-jun Oh

Byung-keun Hwang

Jeom-Jae Kim

Seo-Woo Nam

Andrew Tae Kim

Young-Jin Wee

Jung-deog Lee

Il-young Yoon

Hyo-Jeong Kim

Dong-Myoung Kim

Yong-Ho Kim

Su-Jin Hwang

Sung-Hon Chi

Yong-Jin Chung

Ju-Beom Yi

Hyo-Jeong Moon

Woo-Choel Noh

Mike (j S) Lee

Dong-Whan Ko

Sang-doo Kim

Bong-seok Suh

Chung-Ah Lee

II-Young Yoon

Jae-yeol Maeng

Kwang-Hyeon Baik

Il-whan Oh

Kyoung-Woo IntellPropTeam SemiconductBusin Lee

Jae-Hak Kim

A display apparatus includes a substrate including a display area having a subpixel and a non-display area surrounding the display area, a driving transistor and a light emitting diode provided at the subpixel, a gate driving unit provided in the non-display area, and a link line provided in the non-display area and connected to the gate driving unit, wherein the link line includes a first link portion of a first direction, a second link portion of a second direction, and a third link portion connecting the first link portion and the second link portion and having a substantially curved shape.

Display device including gate driving circuit and link line

A display apparatus according to the present invention comprises a substrate including a display area having a plurality of sub-pixels and non-display area surrounding the display area; a shielding layer on the substrate; a driving transistor in the sub-pixel above the shielding layer, the driving transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode; a light emitting diode in each sub-pixel; and a plurality of signal lines in the non-display area; wherein the signal line includes a first line and a second line, the first line being made of same material as the shielding layer, and the second line being made of same material as the gate electrode.

Display apparatus having narrow bezel

In a method of manufacturing a semiconductor device, an insulating interlayer is formed on a substrate. The insulating interlayer is partially removed to form an opening. A barrier conductive layer is formed on a sidewall and a bottom of the opening. An RF sputtering process and a DC sputtering process are performed independently on the barrier conductive layer to form a seed layer. A plated layer is formed on the seed layer.

Methods of manufacturing semiconductor devices

A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.

Method for fabricating semiconductor device that includes forming passivation film along side wall of via hole

A gate drive circuit for a display device is disclosed, by which output states of scan pulses are identically maintained in a manner of minimizing load deviation between connecting units. The present disclosure includes at least two clock transmission lines transmitting at least two clock pulses having a phase difference in-between, a shift register outputting scan pulses sequentially based on the clock pulses transmitted from the clock transmission lines, and a plurality of connecting units connecting the clock transmission lines to the shift register, respectively, wherein at least one of the connecting units is zigzagged in part, the at least one connecting unit comprising: a pad connected to the corresponding clock transmission line via a pad connecting unit; a zigzagged line connected to one side of the pad; and a connecting line that has one side connected to the zigzagged line and the other side connected to the shift register.

Gate drive circuit for display device

A display device, which includes a plurality of pixels; a data driver for outputting data signals to the pixels; a bias current outputting unit for outputting a bias current having a predetermined magnitude; a plurality of driving current outputting units for outputting driving currents to the pixels; and a first switch connected between the bias current outputting unit and the driving current outputting units for selecting one of the driving current outputting units to connect to the bias current outputting unit, wherein the magnitudes of the driving currents are substantially the same as a magnitude of the bias current.

Driving current output apparatus, method of manufacturing the same, display device and driving apparatus thereof

Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kstage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q, Q, QBand QBnodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q, Q, QBand QBnodes.

Gate shift register

The invention relates generally to a fuse device of a semiconductor device, and more particularly, to an electrical fuse device of a semiconductor device. Embodiments of the invention provide a fuse device that is capable of reducing programming error caused by non-uniform current densities in a fuse link. In one respect, there is provided an electrical fuse device that includes: an anode; a fuse link coupled to the anode on a first side of the fuse link; a cathode coupled to the fuse link on a second side of the fuse link; a first cathode contact coupled to the cathode; and a first anode contact coupled to the anode, at least one of the first cathode contact and the first anode contact being disposed across a virtual extending surface of the fuse link.

Electrical fuse device

Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the same

A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

Driving circuit of liquid crystal display

A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.

Method of fabricating semiconductor integrated circuit device

The semiconductor device includes a fuse structure disposed on a substrate. An interlayer dielectric disposed on the fuse structure. A first contact plug, a second contact plug, and a third contact plug penetrate the interlayer dielectric and wherein each of the first contact plug, the second contact plug and the third contact plug are connected to the fuse structure. A first conductive pattern and a second conductive pattern are disposed on the interlayer dielectric. The first conductive pattern and the second conductive pattern are electrically connected to the first contact plug and second contact plug, respectively.

Semiconductor device and methods of forming the same

A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target.

Method of manufacturing semiconductor device

A gate driving unit for a liquid crystal display device including a plurality of liquid crystal pixels, first to Nth gate lines, a plurality of liquid crystal capacitors and a plurality of thin film transistors, includes first and second clock signal lines for providing first and second clock signals; first to Nth shift registers respectively corresponding to the first to Nth gate lines, the first to Nth shift registers receiving one of the first clock signal and the second clock signal and outputting first to Nth scanning signals, respectively; a redundant repair shift register as (N+1)th shift register receiving one of first and second clock signals and outputting a repair scanning signal; a plurality of first switches for respectively connecting one of the first and second clock signal lines to the first to Nth shift registers and the redundant repair shift register; a plurality of second switches for respectively switching a connection of the first to Nth shift registers with the first to Nth gate lines; and a plurality of third switches for respectively switching a connection of the second to Nth shift registers and the redundant repair shift register with the first to Nth gate lines, wherein N is positive integer.

Gate driving unit for liquid crystal display device and method of repairing the same

A driving circuit of a liquid crystal display includes: a timing controller to output a gate control signal and a data control signal to control driving of a gate driving unit and a data driving unit and to output digital video data; a pair of gate driving units to be alternately driven by using at least one frame as a period to supply gate signals to gate lines of a liquid crystal panel in-response to the gate control signal; and a data driving unit to supply pixel signals to data lines of the liquid crystal panel in response to the data control signal. Degradation of characteristics of transistors constituting each gate driver can be prevented.

Growing community of inventors

Seoul, South Korea

Hong-Jae Shin